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    5. Calibre RVE

    IC Design

    Calibre RVE

    Debugging the error results of physical and circuit verification is costly, both in time and resources. Calibre RVE provides fast, flexible, easy-to-use graphical debugging capabilities that minimize your turnaround time and get you to “tapeout-clean” on schedule. Better yet, Calibre RVE easily integrates into all popular layout environments, so no matter which design environment you use, Calibre RVE provides the debugging technology you need for fast, accurate error resolution.

     

    Datasheet

    Features & Benefits

    • Seamless automated integration with popular design environments preserves the investment in EDA tools
    • Quick, intuitive debugging in cell/block and full-chip designs reduce debug time and iterations
    • Flexible, customizable interface allows quick, easy selection and sorting of results.
    • Cross probe results between layout, schematic, source netlist, layout netlist and Calibre LVS result files.
    • View all parasitics generated by Calibre xRC™ in the Parasitic Browsing window to see extracted values.
    • Locates and visualizes DFM recommended rules, working with Calibre DFM tools
    • Automated short isolation debugging makes even the most complex power ground short simple to fix.
    • Mark Calibre DRC™ errors as fixed or waived for subsequent runs.
    • Fast and intuitive hierarchical SPICE browser for source and layout netlists

    What others say about Calibre RVE

    “I was using a previous version of Calibre. I had a complex lvs problem that I was having difficulty locating where the problem was. A Mentor AE recommended I upgrade to the latest version which had lots of improvements in the GUI and reporting of errors. The new Calibre RVE/LVS took me right to the coordinates of the violating instance, and I was able to see the short right away. And it told me exactly which node it was shorted to. I would certainly encourage Calibre users to look into upgrading to the latest release of the software.”

    Brent Lickiss, Layout Manager, Adesto Technologies

    Checking ESD path resistance in IC designs

    Finding and eliminating ESD issues is critical to ensuring the reliability of IC chip designs. The Calibre PERC reliability platform provides a complete, automated solution for quickly and accurately detecting and debugging P2P resistance violations and bottlenecks in ESD paths, enabling designers to deliver even the largest and most complex IC designs on schedule without compromising performance reliability.

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