- Seamless automated integration with popular design environments preserves the investment in EDA tools
- Quick, intuitive debugging in cell/block and full-chip designs reduce debug time and iterations
- Flexible, customizable interface allows quick, easy selection and sorting of results.
- Cross probe results between layout, schematic, source netlist, layout netlist and Calibre LVS result files.
- View all parasitics generated by Calibre xRC™ in the Parasitic Browsing window to see extracted values.
- Locates and visualizes DFM recommended rules, working with Calibre DFM tools
- Automated short isolation debugging makes even the most complex power ground short simple to fix.
- Mark Calibre DRC™ errors as fixed or waived for subsequent runs.
- Fast and intuitive hierarchical SPICE browser for source and layout netlists
Debugging the error results of physical and circuit verification is costly, both in time and resources. Calibre RVE provides fast, flexible, easy-to-use graphical debugging capabilities that minimize your turnaround time and get you to “tapeout-clean” on schedule. Better yet, Calibre RVE easily integrates into all popular layout environments, so no matter which design environment you use, Calibre RVE provides the debugging technology you need for fast, accurate error resolution.