Signal Integrity Analysis

HyperLynx Signal Integrity

Analyze signal integrity issues early in the design cycle to eliminate costly re-spins.

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Performs signal integrity analysis using automated workflows
Pre-route design exploration
What-if” analysis through detailed verification and sign-off to manufacturing

HyperLynx SI

HyperLynx® Signal Integrity (SI) performs signal integrity analysis using automated workflows that make advanced analysis accessible to everyday PCB system designers. From pre-route design exploration and “what-if” analysis through detailed verification and sign-off to manufacturing, HyperLynx SI has you covered!

HyperLynx SI supports general-purpose SI, DDR interface signal integrity and timing analysis, power-aware analysis and compliance analysis for popular SerDes protocols, all with the fast, interactive analysis and ease of use and integration HyperLynx is known for. Want to reduce your design cycle and increase your chance of first-pass success with your next high-speed design? Use HyperLynx!

Comprehensive SERDES support

HyperLynx® SI supports frequency-domain, time-domain, Channel Operating Margin (COM) and JCOM analysis for over 35 different popular protocols including the Ethernet, OIF-CEI, PCIe, Fiber-Channel, JESD and USB families.

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DDR wizard

Integrated power-aware analysis models interactions between the power delivery network and high-speed signals.

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Integrated full-wave 3D electromagnecic field solver

HyperLynx models key structures in high speed serial links using an integrated 3D solver. For DDR design, an integrated hybrid solver models simultaneous switching noise (SSN) and non-ideal return path behavior for high-speed signals.

Case Studies of PI effects on SI

The interaction between power and signal integrity is often complicated and confusing. With single-ended DDR busses reaching the same data rates as many popular differential SerDes channels, a better understanding of this interaction becomes more crucial. In this paper we discuss some of the primary methods of how power and signal integrity interact with each other, present multiple cases that demonstrate situations where such interactions occur, and offer possible means of mitigation.

Technical Specifications

Industry-renowned ease of use: automated workflows guide users through setup and analysis step by step
Supports HSPICE, ELDO, IBIS-AMI, AMS, S-parameter, IBIS models
Accurate modeling of trace impedance, coupling, frequency-dependent losses
Swept-parameter analysis for trace, via and driver/receiver characteristics
Integrated 2D/2.5D/3D electromagnetic solvers
Tightly integrated with Xpedition and PADS Professional
Works with all major PCB layout systems

Pre-route analysis

Graphical topology editor supports design exploration, schematic validation and constraint definition
Advanced exploratory stackup, trace and via modeling
Supports automated workflows for DDR, SerDes channel analysis and more
Simulates multiple nets simultaneously, with/without crosstalk

Post-route analysis

Automated batch simulation provides full-board verification
Detailed, automated workflows for DDR, SerDes channel analysis and more
Powerful, easy to use multi-board analysis with for EBD and connector models

DDR design

DDRx wizard guides users through detailed signal integrity and timing analysis of complete DDR/LPDDR/LPDDRx interfaces
Supports multiple DDR technologies and adapts analysis flow based on each
Models and analyzes controller-specific timing behaviors and signal integrity requirements
Power-aware analysis models effects of simultaneous switching noise (SSN) and non-ideal signal return paths

SerDes channel design

SerDes Compliance wizard automates analysis workflow with built-in support for over 35 popular serial link protocols
Performs frequency-domain, time-domain and channel operating margin (COM) based analysis
Built-in COM engine runs much faster than traditional script-based tools and doesn’t require additional third-party software licenses
IBIS-AMI model support, including swept-parameter analysis
Accurately and quickly determines worst case patterns, serial interface bit error rates (BER) and associated eye diagrams