Practical Insights for Smarter Enginering; technical Workshop with Inventas, Siemens and InnoFour

 

 

Welcome to an other full afternoon dedicated to FPGA development and verification at Inventas Oslo. Together with Inventas and Siemens, we invite FPGA developers, verification engineers, and digital designers to a free technical workshop featuring hands-on training, practical presentations, and discussions on modern verification methodologies.

 

FPGA verification with advanced debugging, simulation flows and modern test-bench methodologies

 

This time, the program focuses on improving design quality earlier in the development cycle, advanced verification techniques using UVVM and UVM, processor design in VHDL, and how AI-powered verification tools are beginning to change everyday engineering workflows.

The day concludes with an afterwork and mingle session where you can exchange experiences and connect with fellow FPGA professionals. 

 

You will learn:

• How to identify RTL issues before simulation and reduce debug cycles
• Practical methods for improving RTL quality and design-review effectiveness
• Advanced randomization techniques in UVVM
• How to build reusable and maintainable UVM agents
• Design principles behind building a RISC-V processor from scratch in VHDL
• How AI-assisted verification workflows can improve productivity throughout the verification process

 

About the sessions

• Hands-on workshop:

Advanced hands-on workshop: Anticipating Bugs Before Simulation – Early RTL Issue Detection in Practice; by Faïçal Chtourou - DVT Field Application Engineer at Siemens EDA

Building on the previous hands-on workshop, this advanced session moves earlier in the verification flow: from debugging failures to preventing them. Participants will work through practical labs focused on identifying RTL design risks before they reach simulation, including coding-quality issues, structural problems, connectivity mistakes, clock and reset concerns, and implementation-intent mismatches. The goal is to help teams improve RTL readiness, shorten debug cycles, and make design reviews more systematic and effective.

 

Participants should bring their own laptops; all required tools and lab environments will be provided onsite.

 

• Presentation:

Advanced Randomization with UVVM – Smarter Stimulus for VHDL Verification; by Marius Elvegård, Senior FPGA Developer & Discipline leader Digital at Inventas.

 

This session focuses on advanced randomization concepts in UVVM and how structured random stimulus can improve verification quality in VHDL-based environments. We will present practical techniques for controlling value ranges, applying exclusions and weighting, improving corner-case coverage, and keeping test intent readable and maintainable.

 

Building Reusable UVM Agents; Sverre Vigander, Principal FPGA developer and engineer at Inventas, will provide a practical introduction to reusable UVM agents and their role in modern verification environments.

The presentation explores agent architecture, interaction between components, and strategies for creating modular and scalable verification infrastructures that can be reused across projects.

 

• Guest lecture:

Building a RISC-V processor from scratch; Yngve Hafting; Lecturer at the Research Group for Robotics and Intelligent Systems at Oslo University

 

Yngve Hafting from the Department of Informatics at the University of Oslo (UiO) has developed a small RISC-V processor from scratch in VHDL, with a focus on simple and readable RTL. In this presentation, he will take us through the implementation and some of the design choices behind it. He will also explore how full control of the RTL opens up for optimization, custom instructions, and application-specific processor architectures.

 

• Presentation: 

Agentic AI in Questa One – A New Approach to Verification Productivity; by Faïçal Chtourou.

Questa One is a major release for AI-powered, data-driven verification with agentic AI capabilities enabling smarter, goal-driven workflows.

This session introduces the Questa One Agentic Toolkit and explores how agentic AI can support tasks such as RTL creation, verification planning, analysis, debug, and closure. Siemens AI-driven workflows can leverage design context, results, logs, waveforms, assertions, and verification intent to assist engineers throughout verification while maintaining human oversight through review and approval steps. 

 

Practical information

 

This is a collaboration between Inventas, Siemens and InnoFour, combining tools, methodology, and hands-on experience. You can find the complete agenda and other details here. 

 

 

Details

 

When

Wednesday, October 14, 2026

 

Where 

Inventas AS, Kjølberggata 21, 0653 Oslo Norway

 

Time

09:30 - 17:30 hr