With leading C++ and SystemC support, Catapult offers advanced HLS tools for FPGA, eFPGA, and ASIC. Catapult will accelerate your success with solutions for outstanding Quality of Results through physical awareness, low-power estimation-optimization, design checking, lint, formal, and code coverage.
- Native SystemC and ANSI C++ synthesis
- Write 80% less code to save time and make debug easy
- Simulate 100-1000x faster for reduced verification time
- RTL optimized for power, performance, area, and RTL verification
- Tightly integrated formal C property checking for C based verification
The Catapult High-Level Synthesis Tools empowers designers to use industry-standard ANSI C++ and SystemC to describe functional intent and move up to a more productive abstraction level.
From these high-level descriptions, Catapult generates production-quality RTL. By speeding time to RTL and by automating the generation of bug free RTL, Catapult significantly reduces the time to verified RTL. The Catapult Platform pairs synthesis with the power of formal C property checking to find bugs early at the C/C++/SystemC level and to comprehensively verify source code before synthesis.
Catapult’s advanced power optimizations automatically provide significant reductions in dynamic power consumption. The highly-interactive Catapult workflow provides full visibility and control of the synthesis process, enabling designers to rapidly converge upon the best implementation for power, performance, and area.
Physically Aware HLS
As geometries shrink, Catapult keeps pace with design portability, physical downstream data, and exceptional QoR.Read more
Catapult Low-Power HLS
Catapult Low-Power (LP) is the industry’s first High-Level Synthesis (HLS) tool that targets power as an optimization goal. It takes advantage of PowerPro’s best-in-class power…Read more