C++/SystemC HLS

Catapult is the leading HLS solution for ASIC and FPGA. Supporting C++ and SystemC, designers work in their preferred language, moving up in productivity and quality. With 80% less coding, and simulation speeds up to 1,000x faster than Verilog. HLS Design and verification is the edge you need.

I want to know more about C++/SystemC HLS

Native dual-language support of SystemC and C++
Control and predictability required to achieve design closure on complex designs
Comprehensive design management and assembly systems with 10X capacity
Integration with standard functional verification methodologies
Verification-optimized RTL code

Blazing Fast Design, Verification & Implementation

HLS is more than just C++/SystemC to RTL. Catapult delivers ASIC & FPGA “right first time” RTL for design, verification and implementation. Avoid surprises with Design Checking, improve coverage with Catapult Coverage, and close timing on the latest nodes with a multi-VT Physically aware flow.

Native Dual-Language Support of SystemC and C++
C++ or SystemC is a choice that gives teams the flexibility to decide what is the most effective methodology for their design task. Whether it be the superior simulation and verification speed of sequential C++ with the AC data types (hlslibs.org), or explicit concurrency modeling with SystemC and MatchLib (using the AC types), Catapult has you covered.

Catapult Design Checker Finds Bugs Before Synthesis
Find coding bugs before you even knew you had them! Without a testbench and by using a blend of lint and formal engine analysis, Catapult identifies bad logic-creating uninitialized variables, array bounds violations, and other coding problems that can appear in C++ or SystemC. Catapult even provides feedback on potential HLS QoR problems before synthesis.

Catapult Coverage Accelerates Verification Before RTL
Use traditional RTL metrics such as statement, branch, expression, and toggle coverage. Combine with functional verification techniques from SystemVerilog to reach high quality HLS-aware coverage without slow and expensive RTL Simulation. Faster C++/SystemC simulation speeds boost your verification efforts and “right first time” RTL delivery.

C/C++/SystemC HLS

Catapult is the only High-Level Synthesis Platform to natively support both ANSI C++ and SystemC, giving designers the freedom to work in their preferred language and move up to a more productive abstraction level. Abstract models synthesizable by Catapult typically require 80 percent less hand-written code and can simulate up to 1,000 times faster than synthesizable RTL.

From these high-level descriptions, Catapult generates optimized Verilog or VHDL, ready for production RTL synthesis and verification flows. The platform gives designers control over which regions are optimized and the ability to work top-down or bottom-up, which is required for RTL IP integration.

The database and smart caching techniques provide at least a 10X capacity improvement, making the synthesis of large subsystems possible. The synthesized RTL is optimized for power, performance, area, and timing closure. This verification-optimized RTL code is ready to be deployed into corporate verification methodologies, including UVM-based flows.

Eigenvalue decomposition

This report discusses the hardware implementation of “eigenvalue decomposition”. Eigenvalue decomposition is used in a wide range of applications for imaging, communication and audio such as image recognition using KL conversion, high-speed communication using MIMO antenna, and electric/sound wave arrival direction estimation using MUSIC method.

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