PCB Analysis with HyperLynx
HyperLynx is a complete family of analysis tools for high-speed electronic design including electrical design rule checking (DRC/ERC), signal integrity (SI), power integrity (PI) with integrated 2D/2.5D/3D electromagnetic modeling (3D EM).
Simplify post-layout compliance analysis with HyperLynx
The problem: lengthy prototype debugging
Most high-speed serial links don’t get verified once routing is complete because the process is time consuming and skill-intensive – and SI experts are in short supply. As a result, most serial channels are laid out according to rules, verified through manual inspection and released to fabrication without thorough analysis. Unverified channels can result in lengthy (and hectic) prototype debugging, board spins and schedule slips. Until now, there has been no other choice.
The solution: automated post-route verification
This paper discusses an automated post-route verification process with HyperLynx that can verify all the channels in a design for detailed compliance with a SerDes protocol standard – automatically, overnight. This allows designers to find problems early in the layout process when they’re easier to correct, and release designs for fabrication with confidence, knowing all their serial channels have been verified.
Scalable High-speed System Design & Verification
HyperLynx combines ease of use with automated workflows to make high-speed design analysis accessible to mainstream system designers. This allows problems to be identified and resolved early in the design cycle. HyperLynx works with multiple PCB tools and is an ideal addition to any PCB design flow.
View simulation results in graphical and report format, making problems in DC power delivery quick and easy to identify. Predict temperature rise with PI/thermal co-simulation.
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HyperLynx DDR PE was created especially for Altium, Allegro CADSTAR and OrCAD engineers who need powerful analysis of DDR1, DDR3 and LPDDR 1/2/3 designs.
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HyperLynx DRC PE provides a customizable and powerful electrical rule checker for PCB designs created in Altium Designer, Allegro, OrCAD or CADSTAR
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Automated pre- and post-route signal integrity and timing analysis for an entire DDR interface. Power-Aware simulation determines impact of SSN and non-ideal return paths.
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Pre- and poste-route analysis for standards-based serial channels has never been easier. Built-in support for over 35 popular protocols with integrated 3D EM modeling.
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Analyze a design to ensure supply voltages and currents remain within safe limits. Ensure PDN impedance meets requirements for key components.
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Rapidly run complex electrical rules on PCBs to verify corporate- and technology-specific rules of thumb.
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Accurately model power distribution networks and noise propagation mechanisms during both pre- and post-layout phases in the PCB design process.
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Use signal integrity issues early in the design cycle to make key design decisions. Use post-route verification to sign-off a design before fabrication.
Read moreSystem-level, post-layout electrical analysis for high-density advanced packaging
As HDAP designs become more popular, the need for post-layout simulation (analog) and post-layout STA (digital) flows to augment basic physical verification (DRC and LVS) is growing. Mentor provides an accurate, automated flow that generates the required HDAP netlist for simulation/STA to enable HDAP designers to ensure that the HDAP will perform as designed.
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"With HyperLynx PI we can test against the Worst-case scenario and add our own margins to it. Also we don't need to use the EMC labs as often as we did. So time to market decreased.
