PCB simulation solutions for high-performance designs

PCB Analysis with HyperLynx

HyperLynx is a complete family of analysis tools for high-speed electronic design including electrical design rule checking (DRC/ERC), signal integrity (SI), power integrity (PI) with integrated 2D/2.5D/3D electromagnetic modeling (3D EM).

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  • Virtual prototyping cuts cost & design time
  • Minimizing re-spins and eliminating physical prototypes
  • 93% of our customers agree that they save costs and design time
  • As a result the quality of work output improves.
  • Make your company more profitable.

Simplify post-layout compliance analysis with HyperLynx

The problem: lengthy prototype debugging
Most high-speed serial links don’t get verified once routing is complete because the process is time consuming and skill-intensive – and SI experts are in short supply. As a result, most serial channels are laid out according to rules, verified through manual inspection and released to fabrication without thorough analysis. Unverified channels can result in lengthy (and hectic) prototype debugging, board spins and schedule slips. Until now, there has been no other choice.

The solution: automated post-route verification
This paper discusses an automated post-route verification process with HyperLynx that can verify all the channels in a design for detailed compliance with a SerDes protocol standard – automatically, overnight. This allows designers to find problems early in the layout process when they’re easier to correct, and release designs for fabrication with confidence, knowing all their serial channels have been verified.

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Scalable High-speed System Design & Verification

HyperLynx combines ease of use with automated workflows to make high-speed design analysis accessible to mainstream system designers. This allows problems to be identified and resolved early in the design cycle. HyperLynx works with multiple PCB tools and is an ideal addition to any PCB design flow.

HyperLynx Product Family

The HyperLynx family provides a complete analysis flow that combines best-practice design rule checking with comprehensive signal and power integrity simulation. Integrated 3D EM solvers create highly accurate interconnect models.

System-level, post-layout electrical analysis for high-density advanced packaging

As HDAP designs become more popular, the need for post-layout simulation (analog) and post-layout STA (digital) flows to augment basic physical verification (DRC and LVS) is growing. Mentor provides an accurate, automated flow that generates the required HDAP netlist for simulation/STA to enable HDAP designers to ensure that the HDAP will perform as designed.

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Discover how others successfully make use of HyperLynx

Reduce board spins

"With HyperLynx PI we can test against the Worst-case scenario and add our own margins to it. Also we don't need to use the EMC labs as often as we did. So time to market decreased.

Johan Furunas, Westermo

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