PCB Analysis with HyperLynx

HyperLynx is specifically designed to put the right tool into the right hands. It speeds your analysis journey by allowing you to control the tradeoff between analysis speed and accuracy, thereby providing the most accurate simulations at the most appropriate times. HyperLynx capabilities include:

• Design simulation

  Modeling and simulation are used to make design decisions by exploring circuit and layout topologies and their behavior. Simulation provides a "virtual breadboard" where we can connect what we want and how we want, to see how it works. We change the design interactively and resimulate to see the effect of design tradeoffs. HyperLynx simulation reports key design performance metrics that can be compared to required values to determine if the design passes or fails, and by how much.

  Design simulation is performed before PCB layout to define the physical design rules used to place and route the board. When our tools are used for PCB layout, design constraints defined in HyperLynx are carried forward into the PCB layout automatically. Once pre-layout design simulations are complete, expected values for design operating margins are established.

• Performance optimization

  When the design is complex and margins are tight, there may be too many possible design tradeoffs to explore with interactive modeling and simulation. HyperLynx has multiple automated optimizers that will improve design performance based on specific performance metrics. Different methods are used depending on the application and size of the design space to be explored. For uncomplicated cases, swept-parameter analysis is simple to set up and provides results that are easy to interpret. In intermediate cases, expert-based algorithms are used to select design alternative for exploration based on application-specific knowledge. In the largest, most complex cases, response surface techniques are used, with advanced algorithms that automatically manage the tradeoff between properly sampling a large design space and zeroing in on areas of optimum performance. The output from each optimization process is an improved set of design parameters and rules that can be driven into PCB layout.

• Analysis verification

  Verification analysis and simulation are used to ensure that the finished design is ready for the next step of the design process. HyperLynx performs verification at both the schematic and PCB layout level:

  • Schematic verification ensures the captured circuitry is functionally and electrically correct. There's no point in investing time and effort into modeling and simulation if the components are miswired, signals aren't properly terminated, or devices use incompatible voltage levels. Schematic verification allows these (and many other) issues to be identified and corrected up front in the design cycle.
  • Post-layout PCB verification examines the board as it was actually laid out to ensure that design rules were followed properly, and that there are no unintended consequences associated with the final layout. Design rules are imperfect and are often impossible to follow exactly. HyperLynx uses a unique "progressive verification" methodology to perform analysis in stages, each more detailed and accurate than the last. This unique flow resolves as many potential design issues as possible, as quickly as possible, while requiring as little user analysis-specific expertise as possible.

  
  Verification analysis doesn't have to wait until the schematic or board layout is complete - in fact, the earlier analysis is performed in the design process, the better. Sections of the design can be verified and implemented, so that issues can be identified and resolved. Finding problems early means that other sections of the design aren't affected, as is 

HyperLynx is organized into several analysis and verification applications designed to operate as stand-alone solutions, or as integrated components of a complete analysis and verification workflow.

• Rules-based design verification

  Expert rules-based verification replaces traditional manual design reviews with automated scanning of a design based on configurable rules. This identifies possible design issues quickly and accurately, although not everything flagged by a rule-based scanner will be a problem; flagged items need to be reviewed and appropriately acted upon. The benefits of rules-based verification are that the analysis is fast, the results point to specific areas of the design that need review, and the identification of problems occurs much earlier and easier than with modeling and simulation.

  Schematic verification
  HyperLynx Schematic Analysis (HL-SA) ensures that schematics are logically and electrically correct right up front in the design cycle. This prevents errors from being passed into simulation or board layout, where finding those problems would be more difficult and also require subsequent rework of the design.

  PCB layout verification
  HyperLynx DRC (HL-DRC) replaces traditional, error-prone manual visual post-layout inspection with fast, automated analysis that can find issues related to analog, EMI, signal and power integrity, packaging and compliance-based electrical safety problems. HL-DRC creates a detailed list of the issues it finds, along with the ability to display each one and highlight problem areas graphically.

• Analog/mixed-signal analysis

  HyperLynx AMS expands standard SPICE-based circuit analysis to include modeling and simulation of electro-mechanical, thermal and other domains in the broader system context. Driven from the same schematics used for PCB layout and capable of including the effects of PCB layout in simulations, HyperLynx AMS provides a virtual environment for circuit design and analysis that will accelerate your design and verification process.

• DDR design & verification

  HyperLynx SI DDRx provides unique, full-interface verification for DDR interfaces by combining signal integrity simulation with timing analysis to check all signal integrity constraints and timing relationships between signals. HyperLynx performs JEDEC protocol-aware, controller-specific analysis and supports DRAM technologies including DDR3/LPDDR3, DDR4/LPDDR4 and DDR5/LPDDR5.

• Serial link design & verification

  HyperLynx SI GHz makes it possible to verify all the SerDes-based serial links in your designs by combining automated layout extraction and 3D EM modeling with an automated compliance analysis protocol. HyperLynx can perform detailed protocol-specific analysis for over 250 different protocols and variants, providing the broadest coverage of any EDA tool. Even if your design has hundreds of serial links, HyperLynx can analyze them all and tell you which passed, which failed, and by how much.

• General-purpose PI and SI

  Modern designs need power - often lots of it at very low voltages. High power and low voltage means the impedance of the Power Delivery Network (PDN) needs to be very low. HyperLynx analyzes the behavior of your design's PCB at both DC and AC to ensure that components get the power they need, at the voltages they need, at the frequencies they need.

  HyperLynx DC Drop analyzes steady-state current flow to ensure that components receive adequate voltage and that current in power planes and power vias doesn't exceed safe levels. Excess current density can overheat areas of the board and cause board failure.

  HyperLynx Decoupling analysis ensures that transient demands for additional current caused by IC switching behavior will be reliably satisfied. Modern PDN's use a hierarchy of decoupling capacitance to service these demands; component values, routing and placement are critical. HyperLynx models the complete PDN structure to ensure that components will get the power they need to run at full speed.

• Stackup design

  Z-planner Enterprise optimizes the process of defining stackup requirements and documenting those requirements early in the design process, ensuring that pre-layout signal-integrity simulations are based on the most accurate laminate data available using a consistent stackup design methodology.

  Z-planner Enterprise enhances the stackup design process by providing an accurate field solver, a loss-planning environment, and a complete dielectric materials library – all seamlessly interfaced within an intuitive signal-integrity layout. This allows users to model the most accurate stackup possible from the start. Model dual-side copper roughness, calculate trace widths based on material glass-weave and optimize sequential lamination.