Signal Integrity Analysis

HyperLynx Signal Integrity

Pre- and post-layout verification are critical steps in ensuring signal integrity and overall performance in high-speed digital designs, including SerDes channels, DDRx memory interfaces, and general-purpose signal integrity. By performing detailed simulations and analyzing the design before and after layout, designers can identify and address any potential issues and optimize the design for maximum performance and reliability.


Analyze signal integrity issues early in the design cycle to eliminate costly re-spins.

i want to know more about hyperlynx signal integrity
  • Performs signal integrity analysis using automated workflows
  • Pre-route design exploration
  • What-if” analysis through detailed verification and sign-off to manufacturing

HyperLynx SI

Advanced SI for High-Speed Systems Designers

HyperLynx SI is a powerful and accessible signal integrity analysis tool that can help designers optimize their designs for maximum performance and reliability. Its automated flows, detailed reports and waveforms, and focus on standards-based design and compliance analysis make it a valuable tool for any design engineer.

Comprehensive SERDES support

HyperLynx® SI supports frequency-domain, time-domain, Channel Operating Margin (COM) and JCOM analysis for over 35 different popular protocols including the Ethernet, OIF-CEI, PCIe, Fiber-Channel, JESD and USB families.

Learn More

DDR wizard

Integrated power-aware analysis models interactions between the power delivery network and high-speed signals.

Learn More

Integrated full-wave 3D electromagnecic field solver

HyperLynx models key structures in high speed serial links using an integrated 3D solver. For DDR design, an integrated hybrid solver models simultaneous switching noise (SSN) and non-ideal return path behavior for high-speed signals.

Case Studies of PI effects on SI

The interaction between power and signal integrity is often complicated and confusing. With single-ended DDR busses reaching the same data rates as many popular differential SerDes channels, a better understanding of this interaction becomes more crucial.

In this paper we discuss some of the primary methods of how power and signal integrity interact with each other, present multiple cases that demonstrate situations where such interactions occur, and offer possible means of mitigation.

Download White Paper

Fields with * are required

Technical Specifications

  • Industry-renowned ease of use: automated workflows guide users through setup and analysis step by step

  • Supports HSPICE, ELDO, IBIS-AMI, AMS, S-parameter, IBIS models

  • Accurate modeling of trace impedance, coupling, frequency-dependent losses

  • Swept-parameter analysis for trace, via and driver/receiver characteristics

  • Integrated 2D/2.5D/3D electromagnetic solvers

  • Tightly integrated with Xpedition and PADS Professional

  • Works with all major PCB layout systems

Pre-route analysis
  • Graphical topology editor supports design exploration, schematic validation and constraint definition

  • Advanced exploratory stackup, trace and via modeling

  • Supports automated workflows for DDR, SerDes channel analysis and more

  • Simulates multiple nets simultaneously, with/without crosstalk

Post-route analysis
  • Automated batch simulation provides full-board verification

  • Detailed, automated workflows for DDR, SerDes channel analysis and more

  • Powerful, easy to use multi-board analysis with for EBD and connector models

DDR design
  • DDRx wizard guides users through detailed signal integrity and timing analysis of complete DDR/LPDDR/LPDDRx interfaces

  • Supports multiple DDR technologies and adapts analysis flow based on each
    Models and analyzes controller-specific timing behaviors and signal integrity requirements

  • Power-aware analysis models effects of simultaneous switching noise (SSN) and non-ideal signal return paths

SerDes channel design
  • SerDes Compliance wizard automates analysis workflow with built-in support for over 35 popular serial link protocols

  • Performs frequency-domain, time-domain and channel operating margin (COM) based analysis

  • Built-in COM engine runs much faster than traditional script-based tools and doesn’t require additional third-party software licenses

  • IBIS-AMI model support, including swept-parameter analysis

  • Accurately and quickly determines worst case patterns, serial interface bit error rates (BER) and associated eye diagrams

show me how Signal Integrity works for me

Fields with * are required