SI Analysis

SERDES Channel Design and Analysis

HyperLynx delivers advanced functionality to identify issues and optimize the design of SERDES channels. It contains the protocol-specific and EM expertise that hardware design engineers need to extract, model, and design SERDES channels and perform compliance verification. Using channel operating methods, HyperLynx helps hardware design engineers make tradeoffs among channel loss, reflections, crosstalk, and device specifications.

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Return-path aware, automatic channel extraction and modeling
Protocol-specific channel compliance verification
Pre-layout 3D structure experimentation and optimization
FastEye diagram and IBIS-AMI model-based channel analysis

HyperLynx SERDES Channel Design

HyperLynx SERDES Channel Design supports frequency-domain, time-domain, Channel Operating Margin (COM), and JCOM pre- and post-route analysis for over 35 different popular protocols.

Return-Path Aware Channel Extraction and Modeling

HyperLynx eliminates the manual process by automatically dividing the channel to 2.5D and 3D field solvers (for accurate modeling) and synthesizing the resulting models for subsequent time-domain or frequency-domain analysis or compliance verification, all while providing the EM expertise needed for accurate SERDES analysis.

Eliminates the current, multiple-software-based, manual approach for channel extraction and model post-processing
Properly accounts for the location and path of the return signal
Implements “rules of thumb” during port creation, number of mesh elements, and setting of boundary conditions to create accurate, high-frequency S-parameter models
Automated workflows let you offload in-house SI experts and consultants
Automatically applies previously generated S-parameter models to similarly routed configurations to reduce design analysis time

Protocol-specific Channel Compliance Verification

HyperLynx eliminates the time spent reading and the training needed to understand complex and sometimes obscure SERDES specifications. With the use of behavioral models, simulations are easier to set up and run faster than when IBIS-AMI models are used.

Qualify the channel with protocol-compliant buffer and package models
Optimize buffer equalization based on protocol architecture while adhering to constraints such as DFE, CTLE, and FFE
Support for 35+ protocols including PCI Express, Ethernet, USB 3.1, Fiber Channel and OIF/CEI
Automated workflows let you offload in-house SI experts and consultants

Pre-layout 3D Structure Experimentation and Optimization

For SERDES channels, a significant amount of analysis and design space exploration is performed during the pre-layout phase of the design. HyperLynx expedites design setup and topology experimentation by providing templates for commonly used routing topologies. Template-based support for single and differential via pad stacks, BGA breakouts/break-ins, stripline and microstrip routing with and without meshed reference planes, differential vias with DC blocking capacitors, and others.

Parameterize and sweep template variables in a “system of experiments” to identify passing configurations based on user-specified metrics
Sweep resulting S-parameter models to optimize topology for data rate and protocol

Download Whitepaper

The complex task of designing a serialization – deserialization (SERDES) channel has become even harder in recent years. For example, industry protocols such as PCI Express (PCIe) Generation 4 and Universal Serial Bus (USB) 3.1 have doubled their signaling rates in a single technology generation. The increased data rates have forced the industry to adopt new methods, such as channel operating margins, for interface analysis. Yet, to minimize costs, board materials have remained the same as they were in previous generations of technology.