High-Level Synthesis

Low-Power HLS

Catapult Low-Power (LP) is the industry’s first High-Level Synthesis (HLS) tool that targets power as an optimization goal. It takes advantage of PowerPro's best-in-class power analysis and optimization technology by embedded inside of the HLS process, along with unique HLS optimizations, Catapult delivers the low power RTL you need.

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C/C++SystemC HLS with built-in power awareness
Measures and compares power across multiple architectures
Automatically synthesizes low-power RTL with fine grained optimizations

Rapidly explore and optimize for power

Catapult accelerates exploring different architecture tradeoffs and measures the power, performance and area for eacht HLS solution. It automatically performs fine grained power-saving optimizations aimed at minimizing switching activity in the RTL to deliver the greatest power savings.

Catapult Low-Power (LP) is the industry’s first High-Level Synthesis (HLS) tool that targets power as an optimization goal. It takes advantage of PowerPro’s best-in-class power analysis and optimization technology by embedding it at the core of the HLS engine.

This provides a closed-loop optimization flow across power, performance and area from architecture definition to RTL implementation.

A designer uses Catapult LP to explore different hardware architecture and measures the power, performance and area of each solution. Catapult’s interactive analysis tools assist in design refinement. During the synthesis process, Catapult LP automatically performs fine grained power-saving optimizations aimed at minimizing switching activity in the RTL to deliver the greatest power savings.

Design Platform Empowering Designers

Catapult High-Level Synthesis (HLS) has been proven in production design flows with 1,000s of designs and the resulting RTL adheres to the strictest corporate design guidelines and ECO flows. In addition to Catapult HLS, only Catapult has integrated High-Level Verification tools and methodologies that enable designers to complete their verification signoff at the C++ level with fast closure for RTL. Discover this industry leading family of products.

Key Features

C/C++/SystemC HLS with built-in power awareness
Measures and compares power across multiple architectures
Automatically synthesizes low-power RTL with fine grained optimizations
Leverages PowerPro’s deep sequential analysis technology
Sequential clock gating for fine grained power reduction of register, clock tree, and logic power
Loop and memory optimization for architecture exploration and optimization

Push-Button Measurement and Analysis

Using the HLS testbench configuration already used for Verification, Catapult automatically drives simulation of generated RTL solutions. Captured switching data and technology library enable the embedded PowerPro engine to give designers rapid feedback on the approximate power cost of HLS blocks, enabling exploration and architectural optimization.

Automated Sequential Clock Gating Refinement

With the deep sequential analysis capability of PowerPro, Catapult first-pass optimizations are refined for power reduction across the entire design. Enhancements to the RTL are based on observability and stability analysis using testbench switching activity to guide the value of the optimization. Formal verification of RTL to optimized RTL is available.

Exploring low-power architectures

This paper describes, in general, the Catapult flow for exploring low-power architectures, and it discusses in detail the low-power optimization results achieved using the Catapult LP design flow. The case study was conducted using real customer designs. Designs were synthesized using Catapult with and without low-power optimizations turned on.

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