What's new in HyperLynx 2610

 

Join us at this free Expert Series Webinar that provides a comprehensive deep dive into the HyperLynx 2610 release, showcasing how the new updates transform the high-speed design and verification phase.

 

 

 

We will explore the latest SerDes modeling capabilities, DDR5 CUDIMMs batch wizard support, and demonstrate how new DC analysis constraints, coupled with deep Xpedition integration, streamline power integrity verification. The session will also cover the full release of PDN Time Domain (TD) analysis wizard, alongside improvements in the Touchstone viewer and Time-Domain Response (TDR) for faster diagnostic analysis. We will also explore HyperLynx AMS capabilities to boost design throughput with parallel DSE runs and support for discrete and global parameters. Finally, we will highlight how the HyperLynx DRC and Schematic Analysis (SA) releases give users access to automated wizards, and EDM-integrated workflows for multi-board projects, ensuring a faster, more traceable path to design sign-off.

 

What you will learn:

• How to utilize the new generic 100G PAMn models and IBIS 7.2 features for 100G Ethernet and 112G OIF-CEI designs.
• Overview of updated compliance wizards and the latest OIF-CEI-05.2 standards (up to 224G).
• How the new batch support for DDR5 CUDIMMs enables simulation of DDR5 modules above 6400MT/s
• Enhance PI workflows and tracking real-time DC Drop Pass/Fail status directly within Xpedition Layout via new EDM-HL integration
• Improvements in the Touchstone viewer and TDR (Time-Domain Response) for faster diagnostic analysis, as well as the full release of PDN Time Domain (TD) analysis wizard.
• Advanced modeling & solver integration with unified GND plane modeling, automated S-parameter extraction flows, and enhanced 3D parametric modeling
• Significant optimization throughput increase with the parallel DSE processing, reducing the time required for complex design sweeps.
• Accelerating design sign-off with HyperLynx DRC
• Reduce model-creation effort and faster access to component intelligence with HyperLynx Schematic Analysis

Who should attend:
This webinar is tailored for existing customers and professionals involved in high-speed electronic design:

• PCB layout designers
• SI/PI experts
• Hardware engineers
• Engineering managers

 

Details

 

What

Customer Technical Webcast: What's new in HyperLynx 2610

 

When

Thursday, October 22, 2026

 

Where
Online

 

Time
18:00 hr CEST