ModelSim / Questa Core: Advanced Topics

ModelSim® / Questa® Core: Advanced Topics teaches you to capitalize on the extensive capabilities of ModelSim / Questa Core to effectively and efficiently analyze and debug digital HDL designs. Using various ModelSim / Questa Core features and techniques, you will learn how to produce higher performance test benches, more reliable device-under-test models, and greater confidence of simulation thoroughness and completeness.

Hands-on lab exercises reinforce lecture and discussion topics and provide you with tool usage experience under the guidance of our industry expert instructors. You will be presented with real world design challenges, and the tools and support to develop high quality test benches, to stimulate and analyze designs under test and resolve these challenges in a methodical manner.

• Use advanced debugging concepts and methods
• Address advanced design topics and issues
• Take advantage of advanced cross-window capabilities supporting debugging
• Manipulate designs and the ModelSim environment using Tcl/Tk
• Customize design monitors and comparators using Tcl/Tk
• Determine design "Code Coverage" for verification scenarios
• Use ModelSim in debug and performance modes
• Use the Memory and Statistical profiler to find bottlenecks in your code
• Use "Virtual Objects" to explore designs under test
• Perform advanced design probing with "Signal Spy"
• Create and compare multiple data sets
• Use advanced waveform comparison features
• Visualize and debug Finite State Macines with the FSM Viewer
• Use ModelSim for simulating Verilog, SystemVerilog, SystemC, and VHDL designs
• Analyze and improve design and end product performance from high level abstract design description through gate level implementations
• Debug multiple types of specific design errors

Throughout this course, extensive hands-on lab exercises provide you with practical experience using ModelSim software. Hands-on lab topics include:

• Simulating using Tcl commands and a Tcl script
• Using Tcl/Tk to customize ModelSim / Questa Core
• Simulating with Code Coverage and analyzing results
• Using ModelSim in debug and performance modes
• Using the statistical profiler to analyze testbench and design bottlenecks
• Mixed-HDL design probing using Signal Spy
• Waveform comparison
• Perform gate-level timing simulations
• Perform Verilog PLI and SystemVerilog DPI simulations
• Perform causality traceback
• Debugging iteration limit errors
• Debugging logic errors
• Debugging logical unknown X values using the Dataflow window

• Introduction to functional verification
• ModelSim / Questa Core customization with Tcl/Tk
• Code Coverage analysis
• Vopt (performance) mode versus debug mode
• Optimization flows and methods
• Statistical Performance analysis
• Virtual Objects and Signal Spy
• Viewing multiple datasets
• Waveform comparison
• FSM Viewer
• HDL support and gate-level simulation
• Event Tracing
• Selected advanced design debugging techniques using various ModelSim windows

• The student should have VHDL or Verilog knowledge prior to attending this course.
• The student should have beginner ModelSim / Questa Core skills prior to attending this course, or take the ModelSim / Questa Core: HDL Simulation class.