Calibre Vision AI: Turning Billions of DRC Violatins into Actionable Debug

by Avi Wittenberg

 

At advanced nodes, running design rule checks is only part of the physical verification challenge. The other problem starts when the run produces its results.

For large SoCs at 2 nm, 3 nm and similar process nodes, early full-chip DRC runs can generate hundreds of millions or even billions of violations. At that scale, engineers are no longer simply working through an error list. They need to determine which violations share a common root cause, which indicate systematic integration problems, and which can be deprioritized while the design is still evolving. Traditional batch-oriented debug makes this particularly painful because analysis may not begin until the DRC run and result processing are complete.

Calibre Vision AI is designed around this result-analysis bottleneck.

One important change is the use of an OASIS-based results database instead of relying primarily on large ASCII result files. This allows Calibre nmDRC results to be loaded incrementally while the check is still running. Engineers can therefore begin examining violations and detecting major systematic problems before the complete full-chip run has finished. Siemens also reports that the OASIS representation can be substantially smaller: in one cited example, 3.5 billion violations occupied 1.4 GB and loaded in 45 seconds, compared with 71 GB and more than 15 minutes for the equivalent ASCII results.

 

Completeness also matters. Traditional flows may limit the number of reported errors per rule simply to keep result files manageable. That can hide the true distribution of a systemic problem and force additional iterations before engineers understand its extent. Calibre Vision AI provides instance-complete results, retaining violations across cells, instances and hierarchy so the full pattern can be evaluated in the same iteration.

 

The AI component then operates on this result set. Violations with related spatial and contextual characteristics are grouped into Signals, while recurring failure patterns can be further grouped into Signatures. The objective is not for AI to decide whether a layout is correct, but to reduce a massive raw dataset into a smaller number of useful debug entry points. Engineers can then investigate a representative pattern or common root cause instead of repeatedly examining equivalent violations.

There is also a team-workflow dimension. Global check and cell filters allow engineers to isolate relevant rules or partitions, while Signal status tracking and saved workspaces help chip integrators assign specific problem groups to block owners without losing the surrounding debug context.

The practical value is straightforward: Calibre Vision AI does not remove DRC or replace engineering judgment. It targets the increasingly expensive work after and during the DRC run - finding patterns, identifying root causes, distributing work and deciding where engineering effort should go next. As violation counts continue to grow, improving that analysis loop may be just as important to physical verification closure as making the DRC engine itself faster.

 

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