A Hybrid Design Verification Methodology for Increased Coverage and Faster Iterations
70% of signals in today’s PCB designs require layout constraints for high-speed signaling, EMI, or safety requirements. Proper implementation of constraints needs to be verified after layout to minimize the chance of design errors that could require a re-spin. Detailed post-route simulation is expertise and time-intensive, and not all constraints are amenable to simulation. Safety issues like electrical creepage involve complex non-linear phenomena that are not easy to simulate. As a result, most companies dedicate their scarce signal and power integrity specialists to the most challenging problems and use manual design reviews for everything else – a process that is both time consuming and error prone.
This webinar discusses a hybrid approach for post-route verification that quickly and automatically screens designs for potential faults across multiple disciplines. Potential faults can then be reviewed by the designer and further quantified through simulation if necessary. This method permits near real-time checking of layout as the design progresses. It also eliminates the delays and quality issues associated with manual design reviews while providing complete coverage of high-speed, and safety layout constraints to ensure all requirements have been satisfied.
What You Will Learn
- Most commonly found layout problems in PCB designs
- How to detect hidden electrical issues that generate EMI or poor signal quality
- Knowing which PCB checks can be done quickly and easily, in order to identify where to model and simulate effectively
- High-voltage safety issues and why creepage and clearance are important to measure
- The benefits of automating otherwise tedious design inspection
- How to use HyperLynx DRC easily and effectively in any PCB design flow
Who Should Attend
- PCB/System Designers
- Layout Engineers
- CAD teams responsible for sign-off and review
- Electrical Engineers
- Engineering Managers
Live Web Seminar: A Hybrid Design Verification Methodology for Increased Coverage and Faster Iterations
Tuesday 28th of July 2020
3:00PM - 4:00PM CEST
This webinar will discuss the different electrical requirements associated with DDR designs and show how board and system designers can use HyperLynx to perform post-route verification themselves, helping free up scarce SI experts to focus on their company’s most challenging analysis problems.Managing Electronics Systems Design Risk With An Optimized Verification Strategy
This session will cover research on best-practice process strategies to achieve zero-spin results, as well as the inherent risks if these processes are avoided. Later sessions in the series will address specific engineering technologies that could be deployed within any ECAD design flow.