The design effort for more complex FPGAs has been able to scale linearly by increasing design reuse and adopting a well-architected, platform-based design structure. Unfortunately, functional verification has not benefited directly from this approach. One way to address increased design complexity is to supplement traditional functional verification methods with assertion-based verification (ABV).
Today, ABV has been successfully applied at multiple levels of design and verification abstraction—ranging from high-level assertions within transaction-level testbenches down to implementation-level assertions synthesized into hardware.
In today’s FPGA designs we mainly see the usage of two different assertion languages – the Property Specification Language (PSL) and SystemVerilog Assertions (SVA) – where SVA is chosen by almost half of the projects and PSL only by 10%.
Open Verification Library (OVL) maintained by Accellera is a single, vendor- and language-independent assertion template interface for design validation. These assertions are encapsulated inside easy to use components and are ideal for implementation of low level assertion checks.
What You Will Learn
In this session you will learn:
- How to write SystemVerilog Assertions
- How to write PSL
- How to use OVL
- How to analyze all of them
About the Presenter: Stefan Bauer
Stefan joined Mentor Graphics in 2014 for supporting the distribution channel in the whole HDL area with focus on functional verification. Prior to that, Stefan worked as a verification engineer for Ericsson in Nuremberg, Germany. The main focus of his work was verifying parts of an ASIC by using an OVM/UVM test environment. Stefan has a master’s degree in Electrical Engineering from the Friedrich-Alexander-University Erlangen-Nuremberg.
At the beginning of this session, you will get a 30 min introduction presentation about what is Code and Functional Coverage and how to efficiently analyze them.
After that you have the chance to walk through a 1 – 2 hours hands-on online workshop. The system for this workshop will be open until 5pm UTC+02:00 and you can do the lab within that time.
For the introduction presentation:
For the online hands-on workshop:
- Registration with IP address (www.whatismyip.com)
- NoMachine Client (https://www.nomachine.com/download)
- 1 – 2 hours of your time
Tuesday, June 20, 2017
10:00 - 12:00 hr Europe/Berlin