Connectivity Checking for Completion of Layout
Overview
For finalizing a design and for specific design level completion there are several ways to verify the connectivity of traces and planes and other copper on the printed circuit board.
What You Will Learn:
- Evaluating Net Lines
- Plane connections and plane assignments.
- Design Status Report
- On-Line Hazards review: Open Fanouts, Open Nets
- Why run Batch DRC? (Hint: This is the one that tells you the board is fully routed!)
- Reviewing Batch DRC in the Hazard Explorer
Who Should Attend:
- Users that need a deeper understanding of design connectivity evaluation.
- Users that want to understand the various net connectivity checks available in Layout.
- Users that want to understand plane connections.
Products Covered:
- Xpedition Enterprise
- PADS Professional
Details
What
Customer Technical Webcast: Connectivity Checking for Completion of Layout
When
Wednesday the 16th of November 2022
Where
Online
Time
18:00 CEST
By attending this Expert Series webinar, verification, and design engineers will gain valuable insights into the unique strategies and techniques used to debug race conditions, ultimately leading to improved product quality and faster time-to-market.
Distribution of Currents in Via ArraysIt is very common for intuition about the balancing of currents in via arrays to be correct. However, this is rarely the case.