19 August 2011

Live Webcast: Leveraging Questa Verification IP to Achieve More Verification with Less Effort

Verification of IP blocks, subsystems and complete SOCs is a major challenge for the industry today. Many tools and techniques exist to help with this problem including languages, verification methodologies and EDA tools. The industry is standardizing on SystemVerilog to enable modern verification techniques such as assertions, constrained random and functional coverage and methodologies such as OVM and now UVM to provide an infrastructure to leverage that functionality and enable re-use across projects.


On the design side we are seeing increased use of industry standard interfaces to enable the reuse of design IP necessary to compete in the marketplace. This necessitates independent and rigorous testing of design interfaces, but also enables standard verification IP to be created that can be reused across projects.


Mentor Graphics is an independent supplier of verification IP (VIP) covering popular and leading edge industry standard interfaces and fully supporting SystemVerilog, OVM and UVM for simple integration into today’s verification projects.


What You Will Learn

  • What you should be looking for in a modern verification IP (VIP)
  • How VIP can help you achieve more verification with less effort
  • Using VIP to reduce time to debug
  • Reusing verification components in OVM and UVM testbenches
  • How VIP applies to accelerated and formal verification environments

Who Should Attend

  • Design and Verification Engineers and Managers


  • What: Leveraging Questa Verification IP to Achieve More Verification with Less Effort
  • When: Thursday 20th of October 2011
  • Where: Online
  • Time: 16:00 PM CET
  • Duration: 1 hour
  • Registration: Web