Live Webcast: Leveraging Questa Verification IP to Achieve More Verification with Less Effort
Verification of IP blocks, subsystems and complete SOCs is a major challenge for the industry today. Many tools and techniques exist to help with this problem including languages, verification methodologies and EDA tools. The industry is standardizing on SystemVerilog to enable modern verification techniques such as assertions, constrained random and functional coverage and methodologies such as OVM and now UVM to provide an infrastructure to leverage that functionality and enable re-use across projects.
On the design side we are seeing increased use of industry standard interfaces to enable the reuse of design IP necessary to compete in the marketplace. This necessitates independent and rigorous testing of design interfaces, but also enables standard verification IP to be created that can be reused across projects.
Mentor Graphics is an independent supplier of verification IP (VIP) covering popular and leading edge industry standard interfaces and fully supporting SystemVerilog, OVM and UVM for simple integration into today’s verification projects.
What You Will Learn
- What you should be looking for in a modern verification IP (VIP)
- How VIP can help you achieve more verification with less effort
- Using VIP to reduce time to debug
- Reusing verification components in OVM and UVM testbenches
- How VIP applies to accelerated and formal verification environments
Who Should Attend
- Design and Verification Engineers and Managers
Details:
- What: Leveraging Questa Verification IP to Achieve More Verification with Less Effort
- When: Thursday 20th of October 2011
- Where: Online
- Time: 16:00 PM CET
- Duration: 1 hour
- Registration: Web
The size and advanced features in today’s FPGAs have increased dramatically to a point where they can now compete with capabilities traditionally offered by ASICs alone. Accompanying all of these features and capabilities is a complexity in verification which traditional FPGA design flows are generally not prepared to address.
Live Webcast: Industrial-Strength Clock Domain Crossing Verification with QuestaMore than 90% of today’s designs contain multiple clocks, and all such designs can potentially fail if communication between clock domains is not correctly synchronized. This webinar presents Questa CDC Verification and describes how it is used in world-class production verification flows to detect and eliminate potential problems in multi-clock designs.