Low Power Verification with Questa – An Overview
Overview
The increasing demand for high-performance, battery-operated, system-on-chips (SoC) in communication and computing has shifted the focus from traditional constraints (such as area, performance, cost, and reliability) to power consumption.
Having a methodology to verify the low power intent of your design is an important part of verification flow in this ever evolving field.
This webinar presents a step by step guide into low power verification flow where we talk about writing your power intent, static and dynamic checking of you power structures and protocols, effective debug and finally, closing power states coverage.
What You Will Learn
- UPF basics.
- Power elements
- Static and Dynamic low power checks
- Low Power Debug using Visualizer
- Power State Tables
- PST Coverage
Who Should Attend
- IP and SOC Verification Engineers and Leads
- Verification resources new to, or exploring low power verification field.
- Processor verification teams.
- Verification teams working on IPs or Systems, catering processor and mobile communication space.
- Verification Engineers
- Project Leads
- CAD Engineers
Agenda
Introduction to low power verification flow using QuestaSim.
Details
What
Live Webinar: Low Power Verification with Questa – An Overview
When
Monday 27th of April 2020
Where
Online
Time
7:30 AM - 8:30 AM CEST
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