Introduction to Assertion Based Verification presented by Rachid Laaris
Overview
This webinar introduces you to the concept of Assertion Based Verification and shows you the tools to start using the techniques in your design and verification tasks.
You will learn what OVL, PSL and SVA means, how you can write assertions for your code, and how you can simulate with the assertions using ModelSim/Questa and its assertion capabilities. You will also be introduced to the Assertion Thread Viewer, and its use in debugging assertion issues.
What You Will Learn
- What Assertion Based Verification is
- What OVL, PSL and SVA are
- How to simulate assertions using ModelSim/Questa
- How to use the Assertion Thread Viewer
Who Should Attend
- Verification engineers and managers
- FPGA Design and Verification Engineers
Details
What
Live webinar: Introduction to Assertion Based Verification presented by Rachid Laaris
When
Wednesday 6th of May 2020
Where
Online
Time
14:00 - 15:00 hr CEST
This webinar will feature CAM350/DFMStream Release15 which introduces a new Stencil Design Tool Kit, enhancements to Netlist and Design Compare as well as subscription pricing to all the product lines.
Low Power Verification with Questa – An OverviewThis webinar presents a step by step guide into low power verification flow where we talk about writing your power intent, static and dynamic checking of you power structures and protocols, effective debug and finally, closing power states coverage.