22 April 2020

Customizing DDR4 Designs for Cost & Performance


Designers often rely on guidelines provided by controller vendors to drive PCB layout, but following those rules isn’t always possible. DDR layout guidelines can also drive up a board’s manufacturing costs, because they tend to be conservative. Dedicated SI experts have long used pre-layout simulation to develop their own layout rules that optimize design margin and cost for their particular applications, but SI experts are a scarce resource in most organizations.


This webinar will discuss the different design variables that can affect DDR design margin, and show how board and system designers can use HyperLynx pre-layout simulation to develop layout rules will optimize design margins and minimize cost.


What You Will Learn

  • Designing a stackup to meet impedance requirements
  • Balancing inter-trace spacing against impedance and crosstalk
  • Balancing drive strength and inter-trace spacing against crosstalk
  • Using simulation to derive board-level layout rules
  • Predicting design operating margins before layout
  • Optimizing drive strength and receiver ODT settings


Who Should Attend

  • PCB/System Designers
  • Engineering Managers
  • Signal Integrity Specialists
  • PCB Layout Designers




Live Webinar: Customizing DDR4 Designs for Cost & Performance



Tuesday 26th of May 2020






3:00 PM - 4:00 PM CEST