If you are working from home at the moment, we start a new webinar series on the exciting world of HDL simulation and verification, developed for you and your engineering brain!
Do you know how to compile your whole VHDL code without knowing the order of the files? Do you know how to check the performance bottlenecks in your code?
In this first session, we will show you selected ModelSim features and tricks, which you very likely do not know or have not used yet
Bonus material: Do you know our On-Demand Training library?
We will show you how to access hundreds of hours of training videos and online labs where you can enhance your design and verification skills
This live presentation has a limited seat number. After your registration, we will inform you if your seat is booked.
Who Should Attend
- Verification engineers and managers
- FPGA Design and Verification Engineers
Web Seminar: ModelSim Essentials++
Wednesday the 15th of April
2:00 PM - 3:00 PM CET
This session will cover research on best-practice process strategies to achieve zero-spin results, as well as the inherent risks if these processes are avoided. Later sessions in the series will address specific engineering technologies that could be deployed within any ECAD design flow.Save Time Using Constraint Management - A Success Story from RF Laboratories, Inc
Register for this live webinar to see how RF Laboratories, Inc used constraint management to cut down on design iterations, saving time and cost.