Optimizing high-speed vias with HyperLynx Design Space Exploration

17 November 2022

Optimizing high-speed vias with HyperLynx Design Space Exploration

 

 

Summary

 

Designing vias that are as “electrically transparent” as possible is critical for high-speed serial links and DDR interfaces, but the process of analyzing and optimizing high-speed vias is still somewhat mysterious. Via behavior is affected by multiple design parameters (pad/antipad size, differential via spacing, stitching via locations, entry / exit trace characteristics, etc.). The designer’s possible choices are also constrained by other factors (board thickness and cost targets, via styles, materials, manufacturing tolerances, etc.). This makes via design and optimization a complex problem, with a large potential design space that needs to be explored for possible solutions.

 

This webinar outlines a step-by-step methodology for designing a differential via and optimizing the parameters to meet specific goals. HyperLynx Design Space Exploration is used to automatically explore a large design space and identify an optimal solution.

 

What you will learn:

  • Multiple ways to model and analyze vias in HyperLynx
  • How to assess via impedances using TDR measurements
  • How to use HyperLynx 3D Explorer to evaluate design alternatives
  • Setting up and quantifying a large design space for exploration
  • How to use HyperLynx Design Space Exploration to identify multiple optimal designs


Who should attend:

  • System designers involved with serial links and DDR interfaces
  • HyperLynx users involved with via design and analysis

 

Details


What
Expert Series Webinar: Optimizing high-speed vias with HyperLynx Design Space Exploration

 

When
Thursday November 17, 2022

 

Where
Online

 

Time
6:00 PM CET