PCB Signal Integrity for small to medium PCB teams
PCB simulation analysis at every step of the design process has become essential in producing quality boards with less rerun time and cost. With signal integrity processes in your team’s PCB flow, analysis can be done quickly and simply.
In this webinar with live Q&A learn from industry experts all of the best highspeed PCB design tips and tricks.
With premium signal integrity processes, small and medium PCB teams are addressing high-speed PCB problems throughout the design cycle, beginning at the earliest architecture textural stages and moving through post layout verification.
In this webinar, we will learn about the following best practice PCB analysis capabilities for small and medium design teams, and how they can integrate within your PCB design flow:
- Pre-layout signal integrity simulation
- DDR simulation
- Electrical rule checking
- DC drop resistance analysis
- Analog/mixed signal analysis
Who Should Attend:
- Users of any PCB design tool
- Engineers responsible for the full PCB design process
- PCB Design Engineers
- Engineering managers
- Signal Integrity Engineers
- PCB Layout Designers
Live webinar: PCB Signal Integrity for small to medium PCB teams
Tuesday, March 14, 2023
18:00 hr CET
This customer webcast demonstrates how to use IOPT customer flow to create FPGA symbols and parts and then use those to optimize FPGA/PCB interconnect.S-Parameter Basics and Applications Expert Series
For high-speed circuit analysis, S-Parameters of signal traces and interconnect are extremely useful to board designers - as simulation models in the time domain, and useful to quickly visualize insertion loss, return loss, and crosstalk.