Tessent Shell: Introduction to DFT for tile-based design using SSN
Overview
Join us to learn about the Tessent Shell flow for tile-based designs, including different aspects of Design For Test (DFT) insertion.
Tile-based design features several tiles abutted at the chip level, where only the connections between those tiles exist. The Tessent Shell has the capability to test each of the tiles independently, retargeting internal modes from tiles, and creating consolidated patterns to detect faults on tile-to-tile connections.
This webinar introduces the fundamental steps of Tessent Shell flow for tile-based design. It explores in more detail on different aspects of DFT insertion in such designs by introducing a simple tile-based design example.
What You Will Learn:
- How to use Tessent Shell flow for tile-based design
Who Should Attend:
- All Tessent Users and all DFT Users
Products Covered:
- Tessent Shell
- Tessent Scan
- Tessent MemoryBIST
- Tessent BoundaryScan
- Tessent IJTAG
- Tessent TestKompress
Details
What
Customer Technical Webcast: Tessent Shell: Introduction to DFT for tile-based design using SSN
When
Tuesday May 14, 2024
Where
Online
Time
18:00 hr CEST
Join us at this free Expert Series Webinar that will show you the BackDrill process in Xpedition Layout & PADS Professional.
Simulating Silicon Behavior with QuestaSim XpropJoin us at this free Expert Series Webinar as we discuss all the features of xprop as well as demonstrate how to enable it in your design today.