23 June 2009

Tuesday Tech Talk - FPGA Synthesis Techniques for Improving Design Performance

23 rd of June 2009 at 15.30 and 20.00 Central European Time (CET)

FPGAs have come a long way in terms of capacity, performance, and complex feature set. At the same time, FPGA designs continue to stretch the limits of the latest devices and synthesis tools.

This Tech Talk will discuss how synthesis technology has evolved to leverage device capabilities and help meet design closure. Topics will include knowing what optimizations to enable and when, physical synthesis flows to improve timing, graphical analysis to leverage specialized FPGA resources, and incremental flows to shorten run-time.

Who Should Attend

  • FPGA Design Engineers
  • Technical Managers

What You Will Learn

  • RTL coding styles to improve area/timing
  • When to use specific optimizations in synthesis
  • Physical synthesis and embedded resource management to improve performance
  • Incremental flows to preserve QoR over multiple iterations

Upcoming Sessions:

Understanding the Basics of OVM for Verification

Tuesday, July 7
15.30 or 20.00 Central European Time (CET)