HDL Designer 2015.1 Release
We are pleased to announce the production release of HDL Designer 2015.1. This release contains a range of significant enhancements across all 4 key aspects of the tool. A summary can be found below with further details in the “What’s New” presentation provided in the release and also available on SaleConnect.
Please remember that SystemVerilog Assistant, Design Checking and Register Assistant are included in HDL Designer only (not included in HDL Author).
Highlights 2015.1 (* Features included in HDL Designer, not HDL Author)
- SystemVerilog Assistant*
- Option to invoke outside HDL Designer (requires HDL Designer license)
- Significant improvements in invocation speed and time to open large projects
- New “Wrapper Import” from ModelSim/Questa compilation scripts
- Updated UVM Templates
- UVM 1.2 support
- VHDL 2008 Enhancements
- Dialect setting for graphical views
- Support for Unconstrained Record Elements
- Design Checking* Enhancements
- Common GUI and RuleSets for RTL and verification checking
- Matching Ranges rule option to ignore size mismatches of VHDL signed/unsigned expressions
- Unreachable Blocks rule renamed to Reachability with new option to check for Unreachable blocks of code or conditions which are always true
- Register Assistant* 4.6
- RTL pipelining option
- Word addressing option
- UVM Endianess control
- C header overall reset method
- Updated Vendor Flows
- New Xilinx Vivado interface
- Quality Improvements
- Over 65 DRs/ERs have been addressed
Production software can be downloaded from Supportnet at: HDL Designer Series 2015.1
There is no change to licensing.
The 2015.1 release of HDL Designer Series supports the following operating systems:
- Windows XP (32 bit)
- Windows 7 (64 bit) – please note this is a 32-bit executable
- RHEL5 (64 bit) – please note this is a 32-bit executable
- RHEL6 (64 bit) – please note this is a 32-bit executable
For more information regarding this HDL Designer 2015.1 Production Release please contact us.
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