Mentor launches Calibre RealTime Digital to help cut weeks off of IC design signoff
Mentor, a Siemens business, announced Calibre® RealTime Digital – a new physical verification tool that works in concert with popular commercial place-and-route environments to ensure “Correct-by-Calibre” routing, and help design teams cut weeks off of IC signoff.
Calibre RealTime Digital is the sister product to Mentor’s multi-award-winning Calibre RealTime Custom tool introduced in 2011 for custom IC design flows. Targeting the full-chip and block-level digital market, the Calibre RealTime Digital tool is ideal for teams designing primarily ASICs and SoCs for a wide range of end-products including mobile phones, automobiles, wired and wireless infrastructure equipment, and a plethora of industrial and commercial applications.
The new tool helps design teams solve a common problem in the last step of the design process. After performing placement and routing, design teams send their designs through a full DRC (Design Rule Check) verification run, which can take several hours for a billion-transistor design. Early runs often uncover problems in the design, which must be fixed to comply with foundry manufacturing rules. Design teams then go back into their place-and-route tools to fix the problems, and perform a full DRC run once again. They often find that their fixes created additional errors, leading to even more iterations and delays before finally converging on a correct design that’s ready for manufacturing.
The Calibre RealTime Digital tool helps solve these problems by working in concert with place-and-route tools. As design teams use place-and-route to fix violations discovered after full DRC runs, they can use the Calibre RealTime Digital tool to make minor changes, thereby resolving DRC violations without causing additional violations -- ergo “Correct by Calibre”. The Calibre RealTime Digital tool achieves this by making the minor changes and performing customized, smaller and more localized DRC runs to help ensure the violations are removed. Shorter iterations during debug reduce the total number of full-chip pass iterations, allowing designers to dramatically shorten design cycles and get to market sooner.
“Calibre RealTime Digital is an accelerator to our existing physical verification strategies that fits seamlessly into our design flows,” said Weikai Sun, associate vice president of Engineering at Inphi. “We expect the tool will allow us to cut weeks off of our signoff schedule.”
“Calibre RealTime Digital is a solution that was driven by customer requests,” said Joe Sawicki, vice president and general manager of Mentor’s Design-to-Silicon Division. “The tool can save time and headaches for design teams developing system chips using any digital process. By working in tandem with the place-and-route tool, Calibre RealTime Digital helps correct physical violation errors that cannot be corrected using a place-and-route system alone. As a result, customers have the potential to get designs to market weeks faster.”
The Calibre RealTime Digital tool is in production now. For more information about the RealTime Digital tool, visit: https://www.mentor.com/products/ic_nanometer_design/verification-signoff/physical-verification/calibre-realtime-digital.