12 April 2016

New Technical Verification Papers Available

We are pleased to inform you about some very interesting New Technical Verification Papers that are available for you now. Below we have highlighted some interesting articles:


  • An Evaluation of the Advantages of Moving from a VHDL to a UVM Testbench

FPGA designs are becoming too large to verify by visually checking waveforms, as the functionality has become beyond easy comprehension. At Baker Hughes, a top-tier oilfield service company, we primarily design small scale FPGA designs, typically less than 100 thousand gates, but our designs are growing in size and complexity. As well, they are part of more complex systems that require long lab integration times. more info>>

  • Increased Efficiency with Verification Run Manager (Questa® VRM)

For all the incredible technological advances to date, no one has found a way to generate additional time. Consequently, there never seems to be enough of it. Since time cannot be created, it is utterly important to ensure that it is spent as wisely as possible. Applying automation to common tasks and identifying problems earlier are just two proven ways to best utilize time during the verification process. Continuous Integration (CI) is a software practice, which is focused on doing precisely that, resulting in a more efficient use of time. more info>>

  • Simplified UVM for FPGA Reliability: UVM for "Sufficient Elemental Analysis" in DO-254 Flows

DO-254 and other safety critical applications require meticulous initial requirements capture followed by accurate functional verification. “Elemental Analysis” in DO-254 refers to the verification completeness to ensure that all ‘elements’ of a design are actually exercised in the pre-planned testing. Code Coverage is good for checking if implementation code has been tested, but cannot guarantee functional accuracy. Currently, functional accuracy is guaranteed using pre-planned directed tests, auditing the test code and auditing the log files. This is not scalable as designs get complex. In this article we will look at using SystemVerilog syntax to concisely describe the functional coverage in the context of accurate “elemental analysis”. more info>>


Via this link you can read all the new interesting articles. And of course, if you want additional information or have questions, don't hesitate to call or email us.