Top Most Read White Papers in 2015
- MAD FLOTHERM - "10 Tips for Predicting Component Temperatures… A High-Level ‘How To’ Guide"
Component temperature prediction is important from a number of points of view. Historically component temperature has been correlated with reliability, with early studies relating field failure rates to component temperature. More recently physics-based reliability prediction has related failure rates of electronic assemblies to the magnitude of temperature change over an operational cycle (power-on, power-off, power-on…), and rate of temperature change, both of which are influenced by steady-state operating temperature. Failures are often attributed to solder joint fatigue. In some applications, like computing, CPU speed is adversely affected by temperature, and in other cases components have to run at very similar temperatures to avoid timing issues. High temperatures can cause operational issues, such as latchup. Whether the intention is to increase reliability, improve performance, or avoid problems during operation, accurate prediction of component temperatures helps thermal designers to achieve their goals. More >>
- PADS FLOW - "Eight Steps for Ensuring PCB Design Success"
Printed circuit boards are the backbone of electronics products, providing the electrical system upon which the performance, life span, and reliability of the end product depend. When designed correctly, products with high-quality circuitry will have lower field failure rates and fewer field returns, resulting in lower cost and higher profit for you. This paper discusses the eight steps you can take to ensure PCB design success. “PADS is very easy to get up and running with a design, yet has enough advanced features to support more complex designs” - Matt Karger, Hardware Engineer, The University of Texas at Austin, TechValidate ID: 271-D46-B8E “I am able to do anything I need to get done with PADS. There is enough flexibility to conquer any design challenge.” - TechValidate ID: CDD-6CF-65A PADS is superior to other desktop PCB routing tools. Easy to set up and learn. Faster. Better results. - Dinesh Chandra, Hardware Manager, Socomec Group, TechValidate ID: B3E-661-20C. More >>
- XPEDITION FLOW - "Six Principles of Easy-to-Use PCB Design Creation"
Typically, design engineers spend only a fraction of their time with EDA tools. So, to help optimize every minute these engineers spend in the design-creation process, we have come up with a list of six principles that design tools should adhere to. We then take a look at real-world functionality that can meet these ease-of-use principles. More >>
ANALOG FASTSPICE - "Ten Common Device Noise Analysis Mistakes"
Device noise is critical in nanometer-scale CMOS processes, and it fundamentally limits the performance of many circuits at 45 nm and below. Given the right tools, device noise analysis (DNA) is a fairly straightforward process that should produce results that are within 1 dB to 2 dB of silicon measurements. However, there are a number of common mistakes that can lead to grossly overestimating or underestimating the device noise impact—leading to substantial over-design and under-design. There are three basic types of DNA. Transient noise analysis is a statistical time-based technique that applies to every type of circuit. Transient noise analysis is the only device noise analysis applicable to non-periodic circuits. For periodic-driven circuits, such as charge pumps and switched-capacitor filters, periodic noise analysis is generally much faster and provides better diagnostic information than transient noise analysis. Similarly, for periodicautonomous circuits, oscillator noise analysis is much faster and provides better diagnostic information (e.g., device contribution and sensitivity analysis) than transient noise analysis. Since transient noise analysis is applicable to all types of circuits, it provides a good way to cross-check results for periodic circuits and oscillators. Used correctly, all of these techniques should produce results within 1 dB to 2 dB of silicon measurements. More >>
- TANNER - "Full-Flow Tool Suite for both Custom Analog and Mixed-Signal Designs"
The Tanner EDA AMS IC design flow offers a cohesive, integrated mixed-signal design suite that is ideally suited to IoT and project-based design with its extremely short cycle times and sensitivity to cost. Learn more about the Tanner AMS solution in this white paper. More >>
IC D2S CALIBRE NMLVS - "LVS Boxing Helps Designers Knock Out Designs Quickly"
Keeping up with the constant demand for better, faster design flow performance while preserving the original layout hierarchy of a design can be very challenging during design verification. Designers must constantly manage tradeoffs between performance, database size, and accuracy. In the early design cycle, using the LVS boxing capabilities of Calibre nmLVS to replace incomplete or missing blocks can help designers reduce the need for expensive high-performance computing resources, as well as the time needed to run interim LVS comparisons, while still providing the necessary design information to downstream flows. By eliminating the unnecessary distractions inherent in incomplete designs, LVS boxing allows design teams to speed up design development and make more effective use of their expensive computing resources, “saving” that time and those resources for the final full-chip tapeout verification. More >>
- TANNER - "Dedicated ASIC Design Is Now Cost Effective, Due To Readily Available Production Capacity, Low Cost Tools And Lower Priced Masks"
Current market and technology trends have increased the demand for mixed-signal ASICs. Smaller projects with modest design budgets are viable due to low cost design tools and easy access to flexible, mature IC processes. This is especially compelling for developing mixed-signal ASICs for cost-sensitive sensor applications for the Internet of things (IoT). This paper discusses how costs and risks can be reduced using multi-project wafer services, coupled with affordable design tools for developing mixed-signal ASICs, like Tanner L-Edit IC. More >>
- PADS FLOW - "Are Your PCB Design Tools up to Speed? (A Comparison)"
This new white paper compares the capabilities of PCB design tools to help your team decide which one best fits your needs. See how your PCB design tool stacks up with the others in this complimentary white paper. More >>
- ANALOG FASTSPICE - "Analog FastSpice Platform Full-Spectrum Sampled Periodic Noise Analysis"
Many high-performance analog/mixed-signal ICs include track-and-hold circuits to sample analog signals at one or more discrete timepoints per period. Although track-and-hold circuits are periodic, traditional periodic noise (pnoise) analysis does not apply because it measures the device noise impact integrated over an entire period rather than at instantaneous time points within the target period. A different technique — sampled periodic noise (a.k.a., sampled pnoise) is required. Application areas include analog-to-digital converters (ADC), delta-sigma modulators, and CMOS image sensors. More >>
- ANALOG FASTSPICE - "Full-Circuit ADC Verification with Analog FastSPICE"
Analog to Digital Converters (ADCs) are critical components in high-speed, high-resolution applications where an analog or RF signal has to be processed, stored, or transported in digital form. ADC performance requirements vary by application and include resolution, dynamic range, linearity, power consumption, speed, bandwidth, SNDR (Signal-to-Noise and Distortion Ratio), and ENOB (Effective Number of Bits). Designers face a wide variety of challenges in verifying ADC functionality against performance specifications. Converting a continuous analog signal into a discrete digital code yields unavoidable approximation errors due to quantization noise, which designers can minimize by choosing the most appropriate architecture for their application. In nanometer technology nodes, ADC performance is also significantly impacted by device noise, postlayout parasitics, process variability, and device mismatch. More>>
- HYPERLYNX - "DDR4 Board Design and Signal Integrity Verification Challenges"
This paper, originally presented at DesignCon and nominated for a best paper award, includes an investigation of DDR4's Pseudo Open Drain driver and what its use means for power consumption and Vref levels for the receivers. This paper also examines a DDR4 system design example and the need for simulating with IBIS power aware models versus transistor level models for Simultaneous Switching Noise characterization. More >>
- CAPITAL - "Make Every Engineer a Cost Engineer"
Modern automotive platforms support hundreds of end-customer features across thousands of configurations, suffer high rates of design change and are designed in ever-decreasing design cycles. This creates an overwhelming design challenge that is highly error prone and impossible to optimize for minimum cost. A change of paradigm is needed. This paper shows the importance of providing feedback and automation within the engineer’s design environment, thus enabling them to be a cost engineer. The goal is to free the engineer from time and creativity sapping processes and allow them to truly innovate. More >>