Universal Verification Methodology
Advanced verification methodologies like UVM (Universal Verification Methodology) enable higher level efficiency and re-usable structure. However many product teams do not take such productivity and quality benefits because they overestimate the ramp-up time required to introduce UVM. In order to increase the time-to-productivity Mentor Graphics created a framework. The so called UVM Framework provides a set of common UVM based testbench building blocks that are ready to use without the necessity of detailed UVM knowledge.
The Mentor Graphics UVM Framework provides a code base used to implement verification infrastructure, interconnect, and operation. Leveraging the Mentor Graphics UVM Framework enables a verification team to develop an operational UVM based simulation environment within a couple of days. This allows the verification team to focus on verifying product features, including writing constraints to characterize stimulus, creating predictors as reference models and defining coverage models.
During the following events you can learn how this UVM Framework can also be deployed in your verification process:
- FPGA World in Stockholm, 8 September 2015
- FPGA World in Copenhagen, 10 September 2015
- Online Web Seminar, 15 September 2015
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