Accelerating FPGA and Digital ASIC Design

Efficiency and quality are both a question of overview, readability, extensibility, maintainability, and reuse, - and a good architecture all the way down is the answer. This applies to both Design and Verification.

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  • Duration: 4 half days
  • Location: Live Online (Instructor-led)
  • Price: EUR 1,450


Digital design for FPGAs and ASICs has a huge improvement potential with respect to development time and product quality. A lot of time is wasted on inefficient design, lack of awareness around this, and knowledge of the most critical digital design issues. This also seriously affects the quality of the end product. The good thing is that this huge improvement potential can be realised just by making a few important changes to the way we design.

The most important design issues to improve are:

  • Design Architecture & Structure
  • Clock Domain Crossing
  • Coding and General Digital Design 
  • Reuse and Design for Reuse
  • Timing Closure
  • Quality Assurance - at the right level 


See the complete course description here

In General

There will be a few examples of quite common bad design approaches- as this is very useful as an eye opener, - and then of course more examples of good approaches for architecture, CDC, Coding, Reuse, etc.

The main focus of this course is quality and efficiency improvement, making you a better designer and your company a better product development organisation. 

80-90% of the course is HDL independent. VHDL is used where code examples are needed, but most of this will be directly transferable to Verilog or SystemVerilog.

The presentation and material will be in English.

Presenter is Espen Tallaksen, FPGA-expert and the architect of UVVM.

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