On average half the development time for an FPGA is spent on verification.
It is possible to significantly reduce this time, and major reductions can be accomplished with just minor adjustments. It is all about Overview, Readability, Maintainability and Reuse at all levels – and you achieve all of this with the right methodology and a good structured architecture.
This is a 3-day course in FPGA-verification – on how to reduce development time and at the same time improve the quality. This is also a unique opportunity to learn the newly open sourced Universal VHDL Verification Methodology (UVVM).