On average half the development time for an FPGA is spent on verification. It is possible to significantly reduce this time, and major reductions can be accomplished with minor adjustments. This is an intensive 3-day course on how to reduce development time and at the same time improve the quality.
The main differentiators between this and other similar courses are the focus on simplicity and the very structured approach to reuse - also inside a single project. We have seen and heard of many complex testbenches by various designers. A major problem with most of these testbenches seems to be that it gets too complex for everybody apart from the VHDL expert who designed it, – sometimes a person with a far more than average interest in the language or system details.
This course is based on the principles of ‘maximum cohesion & minimum coupling’ and ‘Divide and Conquer’, where the test case writer doesn’t have to know anything about the testbench implementation details, and the testbench implementer has a structured architecture all the way down. This approach to VHDL testbenches typically leads to man-hour savings of 20 60% and more, and is unique for this course.
This course is hosted by Espen Tallaksen, EmLogic