Advanced VHDL Verification - Made Simple

Learn the world-wide #1 VHDL Verification Methodology from the creator and main architect of UVVM.


Efficiency and quality are both a question of overview, readability, extensibility, maintainability and reuse - and a good architecture is the answer. This applies for both Design and Verification.



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  • Duration: 5 half days
  • Location: Live Online (Instructor-led)
  • Price: EUR 2.100

Course Overview

On average half the development time for an FPGA is spent on verification. It is possible to significantly reduce this time, and major reductions can be accomplished with minor adjustments. This is an intensive 3-day course on how to reduce development time and at the same time improve the quality.

The main differentiators between this and other similar courses are the focus on simplicity and the very structured approach to reuse - also inside a single project. We have seen and heard of many complex testbenches by various designers. A major problem with most of these testbenches seems to be that it gets too complex for everybody apart from the VHDL expert who designed it, – sometimes a person with a far more than average interest in the language or system details.

This course is based on the principles of ‘maximum cohesion & minimum coupling’ and ‘Divide and Conquer’, where the test case writer doesn’t have to know anything about the testbench implementation details, and the testbench implementer has a structured architecture all the way down. This approach to VHDL testbenches typically leads to man-hour savings of 20 60% and more, and is unique for this course.

This course is hosted by Espen Tallaksen, EmLogic

You Will Learn How To

It is actually possible for almost all companies to speed up the FPGA verification and at the same time improve the FPGA quality and fault coverage. Learn how to build your testbenches in a structured way, which is the key to overview, readability, extensibility, maintainability and reuse. Theory is mixed with practical examples and handson tutorials. The course will also cover important general verification issues like:

  • Using sub-programs and various important VHDL constructs for verification
  • Handling simple verification in a simple manner
  • Making self-checking testbenches
  • Using logging and alert handling
  • Applying standard checkers for value and stability, and for waiting with a timeout for events
  • Using simple procedure based transactions like uart_transmit() and avalon_read() for simple verification scenarios
  • Making your own Bus Functional Model (BFM) – and adding features to speed up verification and debugging
  • Getting a kick start on BFMs with UVVM’s open source BFMs for Avalon, AXI4- full(lite/stream, UART, SPI, I2C, etc
  • Making directed or constrained random tests – and knowing where to use what - or a mix
  • Applying specification coverage (aka requirements coverage)
  • Using verification components and advanced transactions (TLM) for complex scenarios
  • Target data and cycle related corner cases and verifying them
  • Learning to use UVVM to speed up testbench writing and the verification process
  • Getting a kick start on your testbench by using available UVVM
  • Verification components for AXI4 full/lite/stream,
  • Avalon MM, SBI, SPI, I2C, UART; - and use these as
  • templates for your own VVCs
  • Making a new UVVM Verification component in 30 minutes
  • Understanding and using Scoreboards and models
  • Making an easily understandable and modifiable testbench even for really complex verification – and do this in a way that even SW and HW developers can understand them

Guided Labs

The course will be approximately 50% theory and 50% hands-on. You will start by building a rather simple selfchecking testbench, and then add procedures to simplify it, add Bus Functional Models to access your interfaces and add important functionality to these to speed up the verification process. Then you will write a test sequencer to control already available VHDL Verification Components (VVC) and experience how very easy that is.

The next step is to add commands to an existing VVC and control constrained random stimuli and specification coverage, and finally you will generate and adapt your own VVC from scratch. Using a scoreboard and a model is also included in the labs.

All participants must bring their own PC with their own preferred simulator (Questa, ModelSim, Riviera-PRO or Active-HDL). This allows an easy continuation after the course is finished.

UVM for VHDL - only much simpler

To be fair - UVM is significantly more advanced than UVVM in some areas, but for the huge majority of testbenches that extra functionality does not yield higher efficiency or quality. In fact, that extra complexity most often results in slower development and a verification system that is too complex for most of the FPGA development team. UVVM on the other hand is just a logical extension on VHDL, and thus a logical extension for VHDL designers, who can implement this step by step - when they see the need for more functionality.

UVVM also allows VHDL developers to continue using fairly inexpensive VHDL tools rather than the much more expensive SystemVerilog and UVM related tools, and includes the following:

  • the most important UVM functionality, but extremely simplified for the user,
  • the modular approach of a good FPGA design, with a hierarchical testbench structure that mirrors the design structure,
  • a standardised VHDL testbench architecture and a standardised VHDL Verification Component architecture,
  • a pure VHDL approach
  • the lowest possible user threshold for the functionality you need
  • no lock-in, but the user can pick any one or more procedures, functions, BFSs, VVCs, and support functionality
  • randomisation and specification coverage

UVVM will be used as example throughout the presentations and labs, but the principles taught and shown are general state of the art VHDL verification methodology. Hence you basically get 2 courses in one:

  • General VHDL verification course with best practices for making good testbenches
  • UVVM course – enabling the best possible VHDL testbench infrastructure and architecture

Target participants

The course is aimed at FPGA designers and verification engineers with a good knowledge of VHDL and some experience with VHDL testbenches and verification. You should also have working knowledge with Questa, ModelSim, Riviera-PRO, Active-HDL or other simulator. (The course if equally relevant for ASIC designers using VHDL for verification)

More information and the agenda can be found here

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