ModelSim / Questa Core: HDL Simulation

ModelSim / Questa Core: HDL Simulation teaches you to effectively use ModelSim / Questa Core to verify VHDL, Verilog, SystemVerilog, and mixed HDL designs.

You will learn how ModelSim / Questa Core supports HDL behavioral simulations, and some basic concepts in the digital design flow.

Hands-on lab exercises will reinforce lecture and discussion topics and provide you with extensive tool usage experience under the guidance of our industry expert instructors.

• Invoke the ModelSim / Questa Core program
• Prepare VHDL and Verilog data for use by ModelSim / Questa Core
• Create and use design Libraries
• Use ModelSim / Questa Core commands to run a simulation
• Create a simple simulation script
• Use ModelSim / Questa Core for batch simulations
• Use the ModelSim /Questa Core Graphical User Interface
• Create a ModelSim / Questa Core project
• Simulate VHDL or Verilog designs
• Simulate mixed VHDL/Verilog designs

Throughout this course, extensive hands-on lab exercises provide you with practical experience in using ModelSim. Hands-on lab topics include:

• ModelSim / Questa Core Graphic User Interface
• Invoke and use basic simulation commands
• Create a basic simulation script
• Create data libraries and simulate VHDL and Verilog designs
• Detect Verilog hazards
• Create a VHDL project
• Detect and fix an error in a VHDL design
• Create and simulate a mixed VHDL/Verilog design

• ModelSim / Questa Core User Interfae Windows
• Shell Commands
• Steps to invoke a Design Using ModelSim / Questa Core Commands
• Steps to invoke a Design Using the Graphic User Interface
• The Advantages of using projects
• Libraries in the ModelSim / Queasta Core environment
• Create and simulate mixed VHDL/Verilog HDL designs
• Design Hierarchy / Building and Simulating Designs
• Verilog Hazards

• Hardware, Software and System Engineers who perform VHDL, Verilog or mixed-VHDL/Verilog simulation and analysis.

• Some VHDL or Verilog knowledge
• Some familiarity with digital design concepts