PCB

IOPT FPGA Design Workshop

Experience the benefits of optimizing the FPGA IO in the floorplanner and PCB layout integration for board layout routing improvement.

Duration: 1 day
Location: Almelo - the Netherlands
Price: EUR 650

Course overview

Experience the benefits of optimizing the FPGA IO in the floorplanner and PCB layout integration for board layout routing improvement.

In this workshop, you will experience the benefits of optimizing the FPGA IO in the floorplanner and PCB layout integration for board layout routing improvement. You may choose to utilize corporate library symbols or designer defined symbols created by IOPT

Content

Corporate Standard Library FPGA Symbols

xDX two FPGAs with two hierarchical interface hierarchical functional blocks
xDX FPGA symbols instantiated from library and connected
xDX/IOPT FPGA device definition - integrate into the xDX project ready for IOPT floorplanner optimization
IOPT Floorplanning with multi-FPGA I/O optimization
Integration with layout

Utilize Custom FPGA Symbols

xDX FPGA with hierarchical interface functional block
xDX/IOPT FPGA device definition - integrate into the xDX project ready for IOPT floorplanner optimization
IOPT user custom symbol partitioning, fast symbol creation, and instantiation into xDX
IOPT floorplanning and I/O optimization
Integration with layout Utilize

xDX IOPT is a product to simplify the FPGA on Board design process, benefiting from the total integration with the PADS Professional or Xpedition Enterprise flow and built upon powerful and proven IO Optimization technology.

Prerequisites

PADS Professional or PADS Standard Plus Suite

IOPT is aimed at engineers of varying experience levels with a simple step-by-step wizard that guides you through the FPGA device definition, using HDL and FPGA vendor constraint files as the primary connectivity source, although comma separated spreadsheet and schematic connectivity is also accepted. Once the FPGA is defined it can be loaded into IOPT-integrated FPGA Floorplanner to host the powerful Multi-FPGA optimization process in the context of the PCB layout.

GA Library parts and symbol sets that adhere to the FPGA vendor device pin rules. In specifying your FPGA part definition, you will benefit from a real-time view of your parts symbol set with dynamic update of any of the settings, making a complex, error-prone task a joy to use. If you have specific symbol requirements that differ from the standard Vendor IO Bank representation, you can create your own custom symbols utilizing IOPT symbol generator and publish for the part creator to promote to the corporate library.