PCB

The CES Fundamentals Tips & Tricks

The CES Fundamentals, Tips & Tricks course was developed to provide a practical guideline through the constrained process of your design.

The fundamental part explains the usage of CES and principles in the Expedition Flow. It also provides basic knowledge on the tasks an electrical engineer needs to meet and how this influences the PCB designers demands.

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  • Duration: 1 day
  • Location: Almelo - the Netherlands
  • Price: EUR 650

Course overview

The CES Fundamentals, Tips & Tricks course was developed to provide a practical guideline through the constrained process of your design. The fundamental part explains the usage of CES and principles in the Expedition Flow. It also provides basic knowledge on the tasks an electrical engineer needs to meet and how this influences the PCB designers demands. You will also learn in a task oriented way, how design specifications are converted into constraints. The course will conclude with some practical examples and additional tips and tricks, using a DDR2 example where most of the learned methodologies are passed as a final review.

Practical lab exercises help reinforce what is discussed during the lectures and provide you with the necessary tool use to make your next design more efficiently constrained.

You will learn how to

  • Use CES standalone, from within the frontend, or modified in the backend. And how this all is synchronized in the flow
  • Partition de design based on physical as well as electrical design needs
  • Differentiate between electrical and physical nets and there design criteria
  • Experience the other worlds demands. Meaning for an electrical engineer to see why the layout engineer protests against the requested needs.
  • While the layout engineer is explained the way an electrical engineer makes these requests. And where both parties need to cooperate in an early stage of the design
  • How CES provides the electrical engineer a way to control how correct his constrained are implemented in the Layout and were the implementation is close to the max/min constrained Value. (Delegation is good, control is better)
  • How to enter and reuse previous results with templates

Hands-on Labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience using CES software. Hands-on lab topics include:

  • Who and how to control constraint synchronization
  • Physical design partitioning and stackup interfering with design needs
  • Electrical design constraints and partitioning
  • Practical examples

Intended for

  • Engineers who create schematics that will be used as "front end" designs for Mentor’s Xpedition PCB layout tool
  • PCB Designers who would like to have a good understanding of the constraining Process

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IOPT is aimed at engineers of varying experience levels with a simple step-by-step wizard that guides you through the FPGA device definition, using HDL and FPGA vendor constraint files as the primary connectivity source, although comma separated spreadsheet and schematic connectivity is also accepted. Once the FPGA is defined it can be loaded into IOPT-integrated FPGA Floorplanner to host the powerful Multi-FPGA optimization process in the context of the PCB layout.