The broadest portfolio of hardware design solutions for C++ and SystemC-based High-Level Synthesis (HLS). Catapult's physically-aware, multi-VT mode, with Low-Power estimation and optimization, plus a range of leading Verification solutions make HLS from Siemens more than just "C to RTL".
- Reduces verification cost by 80%
- Production proven flows with thousands of designs
- Formally verifies designs despite language & abstraction differences
To achieve the maximum productivity gain from a C++/SystemC HLS methodology, it is necessary to have the performance and capacity to handle today’s large designs coupled with a comprehensive flow through verification and implementation.
Catapult High-Level Synthesis (HLS) has been proven in production design flows with 1,000s of designs and the resulting RTL adheres to the strictest corporate design guidelines and ECO flows. In addition to Catapult HLS, only Catapult has integrated High-Level Verification tools and methodologies that enable designers to complete their verification signoff at the C++ level with fast closure for RTL. Discover this industry leading family of productsDownload Fact Sheet
A comprehensive HLS solution covering all your needs for the most complex ASIC and FPGA designs.
When it comes to early architecture power estimation, plus optimizing for low-power ASIC RTL, Catapult has what you need.
Physically Aware HLS
As geometries shrink, Catapult keeps pace with design portability, physical downstream data, and exceptional Quality of Results.
The past several years have seen an explosion in the adoption of HLS for chip design driven by increasing design and verification complexity as well as time to market pressures. HLS enables designers to get their chips to market faster by shortening the overall design and verification flow.Complete live seminar recording, slides, resources and more
Catapult Design Checker
Lint and formal analysis to validate your HLS designs for correctness before synthesis.
Avoid design problems and QoR issues that can occur when coding for HLS.
Check the correctness of RTL against your High-Level models using SLEC. Enabling proof that specification and implementation are identical despite differences in language, timing or abstraction.
Provides HLS-aware code coverage including statement, branch, FEC, toggle and array access coverage. SV-inspired functional coverage with support for covergroups, coverpoints, bins and crosses.
Catapult Formal Verification Tools
Formally find mistakes, ambiguities and undesirable design issues, user constraints problems early in the HLS process. Even with differences in timing, and interfaces. Catapult Formal enables verification and coverage closure flow.