Questa Base

Questa Base is the next-generation advanced simulator designed specifically for ModelSim users, leveraging the robust and reliable QuestaSim engine. This advanced tool is packed with new features and enhanced functionality from the acclaimed Questa Simulator family.

Questa Base offers nearly all of the premium features of Questa Core, delivering high-end simulation capabilities while maintaining speeds comparable to ModelSim. In addition, the Visualizer tool, a powerful feature in other QuestaSim products, is now included at no additional cost.

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Superior debug with Visualizer
Reference simulator on LRM compatibility
VHDL, Verilog, SystemVerilog, and mixed language support

Key Features Questa Base

Advanced Optimization Simulation

Harness the power of advanced optimization with vopt and the QIS flow, ensuring more efficient and accurate simulations.
Enhanced Debugging with Visualizer

Experience superior debugging capabilities with Visualizer, Siemens’ premium debugging solution. Now included with Questa Base, Visualizer provides comprehensive debugging tools, allowing you to tackle even the most complex issues with ease.
Assertion-based verification with SVA and PSL

Assertion-based verification (ABV) improves design quality by inserting white-box monitors that provide a window allowing active monitoring of functional correctness. Assertions catch errors that tests activate but fail to propagate to typical black-box observation points, such as the primary outputs
Sophisticated FPGA verification

Questa Base packs unprecedented verification capabilities in a cost-effective HDL simulation solution. Its award-winning single kernel simulator (SKS) technology enables the transparent mixing of VHDL and Verilog in one design.

Assertion-based verification with SVA and PSL

Assertion-based verification (ABV) improves design quality by inserting white-box monitors that provide a window allowing active monitoring of functional correctness. Assertions catch errors that tests activate but fail to propagate to typical black-box observation points, such as the primary outputs. The assertions also turbocharge time-to-debug productivity by identifying functional bugs much closer to the root cause. The time savings from a significantly shorter causality traceback can amount to hours or even days. Questa Base enables ABV by supporting SystemVerilog Assertion (SVA) constructs and the Property Specification Language (PSL). SVA and PSL assertions can be either embedded within the design HDL source code or specified in separate units, then bound to the appropriate module instance in the design hierarchy.

Code coverage

Design verification completeness can be measured through code coverage. Questa Base supports statement, expression, condition, toggle, and FSM coverage. Code coverage metrics are automatically derived from the HDL source. As many design blocks are created to be configurable and reusable and not all metrics are valuable, code coverage metrics can be flexibly managed with source code pragmas and exclusions specified in the code coverage browser.

Premium debug - Questa Visualizer

For years the process of ASIC and FPGA design and verification debug consisted primarily of comprehending the struc¬ture and source code of the design with waveforms showing activity over time, based on testbench stimulus. Today, functional verification is exponentially complex with the emergence of new layers of design requirements (beyond basic functionality) that did not exist years ago; for example, clocking requirements, security requirements, safety requirements, and requirements associated with hardware-software interactions. Given these complex interactions, effective debug often demands experts that are familiar with all the components and a debug environment that is aware of these heterogeneous requirements.

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