Functional Verification

Questa® Power Aware Simulator

The Questa® Power Aware Simulator enables design teams to verify the architecture and behavior of active power management planned for the implementation, but starting much earlier in the design process.

The Questa Power-Aware simulator enables design teams to verify the active power management planned for implementation, but starting much earlier in the design process. Static checks during UPF compilation locate architectural issues, while dynamic checks during simulation find behavioral issues.

Show me how Questa Power-Aware simulator works

Verification of active power management in the post-synthesis Gate-level netlist stages
Verification of active power management at the RTL stage
Achieves the greatest power reduction at the least cost

Very active power management

Verification of active power management at the RTL stage makes it possible to explore alternative power management approaches long before implementation begins, to achieve the greatest power reduction at the least cost. Verification of active power management in the post-synthesis Gate-Level netlist stages makes it possible to ensure that synthesis and manual transformations have correctly preserved the active power management architecture and its behavior.

Questa Power-Aware simulator

Effects of active power management on the design’s structure and behavior are reflected in the waveform, schematic, and power state/transition views. The Questa Power-Aware simulator automatically detects power management errors in both the architecture and behavior of the power management system.

Automatic detection of power management errors

Dynamic and static checking

Automatically detects power management errors in both the architecture and the behavior of the power management system. Static checks during compilation of the UPF identify architectural issues, while dynamic checks during simulation identify behavioral issues.
Power state/transition coverage data collection

Integration with verification

Power states and transitions are recorded in the Unified Coverage DataBase (UCDB) for integration with verification planning and management. This data enables incorporation of power-aware simulation goals into the verification plan so they can be tracked for coverage closure.
Visualization and debugging

Ease of use

Three views (waveform, schematic, and power state/transition) enable designers to find and resolve issues in the power management system quickly and efficiently.

How Questa Power Aware Simulation Works

Given a description of power intent expressed in the industry-standard Unified Power Format (UPF), the Questa Power Aware Simulator

partitions the HDL design into power domains,
adds isolation, level-shifting, and retention cells, and
integrates the power supply network into the design to power each domain

The augmented HDL design can then be simulated with full control over the power state of each domain, for accurate modeling of the effects of active power management on the design’s functionality.

Cross coverage of power states

A power domain is a collection of HDL instances that are treated as a group for power-management purposes.

In this paper, we would build on the methodology devised for state and transitions coverage of power states to define a new metric that captures these requirements. We name this metric as cross coverage of power states. In our opinion, this metric is more meaningful in capturing coverage of interdependent systems/subsystems. For the lack of space we would restrict the scope of this paper to power domains only. However, the same approach can be applied for supply sets also.

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