Supports Flexible Mixed-Signal Verification Methodology

Questa ADMS Simulation

Extending the Questa verification platform to include verification of circuits that contain analog IP, the Questa ADMS tool combines several high-performance simulation engines in one efficient tool, and supports every major hardware description language and exchange standard.

  • Event-driven verification models that are simulated directly in a high-speed for the fastest possible simulation
  • Continuous time AMS verification models for analog applications where high accuracy is necessary
  • Co-simulation between the digital RTL description and the analog SPICE design

Digital Verification for AMS

  • SystemVerilog and UVM with mixed-signal extensions
  • Effective functional verification in presence of analog signals
  • Fast event-driven and real number verification modeling
  • Accurate AMS verification modeling
  • SVA applied to analog signals
  • Familiar Questa debugging environment

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Analog Design and Verification for AMS

  • Analog testbenches applied to mixed-signal designs
  • Effective corner analysis in presence of digital signals
  • Familiar EZwave waveform display
  • Visual debugging of current contributions

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