Questa Visualizer Debug

High performance, scalable, context-aware debug supporting the complete logic verification flow including simulation, emulation, prototyping, testbench, low-power, and assertion analysis. Intuitive and easy to use, Visualizer improves debug productivity of today's complex SoCs and FPGAs

 

Debug & Functional Coverage

High-performance debug environment for digital design and verification, with SV/UVM debug for complex testbenches.

Wave with Transaction Coloring and Biometric Search

RTL DEBUG

Class object handles from the driver in a UVM testbench. These are all the transactions that were sent from the sequencer to the driver. The Virtual interface is also shown, along with the transactions from the channel. Additionally the values displayed are colored according to the biometric searches that have been created.

View Fact Sheet

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TimeCone

ROOT CAUSE ANALYSIS

The Visualizer Debug Environment allows you to find unknowns (X values), trace an event back in time to the root cause of that event through multiple clock domains and find origins of unknowns using the Time Cone window.

Connectivity Tracer

CAUSALITY TRACING

Automatic fan-in display using signal highlight from a signal back to the next primary input or flip flop.

Logic Cone

PHYSICAL CONNECTIVITY

The Logic Cone window allows you to explore the “physical” connectivity of your design, to trace signals that propagate through the design, and to identify the cause of unexpected inputs, by showing a graphic view of the RTL objects in your design.

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