Questa Design Solutions

AUTOMATED INTENT-FOCUSED VERIFICATION FOR DESIGNERS

Questa Design Solutions works with you from design creation through completion with a minimal set of additional inputs. Nothing more than RTL is required, except for UPF and basic constraints, when necessary.

Questa Lint

STATIC RTL VERIFICATION

Questa Lint provides adaptive, integrated insight to the designer to ensure that the quality requirements and intent are met. Pre-configured methodologies provide immediate, intuitive feedback on design issues.

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Questa AutoCheck

STATIC RTL BUG HUNTING

A fully-automatic formal bug hunting app that finds deeply hidden bugs due to common RTL coding errors, AutoCheck makes it possible to eliminate a wide range of bugs without a testbench.

 

Questa X-Check

X-STATE VERIFICATION

Questa X-Check is an automated application that exhaustively roots out ‘X’ issues without a testbench.

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Questa Clock-Domain Crossing (CDC) Verification

CDC VERIFICATION

Questa CDC finds errors using structural analysis to detect clock-domains, synchronizers, and low power structures via the UPF. It then generates assertions and metastability models for protocol and reconvergence verification.

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Questa Reset-Domain Crossing (RDC) Verification

RDC VERIFICATION

Questa RDC finds errors using structural analysis to detect asynchronous reset domains, synchronizers and low power structures via the UPF. It then generates assertions to exhaustively prove that the design is clean.

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Questa Signoff CDC

SIGNOFF CDC

Questa Signoff CDC builds on Questa CDC RTL analysis and automatically generates and analyzes assertions to rapidly identify chip-killing glitches and other clock-domain crossing issues.

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