Advanced Verification Jumpstart - 10th of February 2010
Duration: 1 Day
Pricing: 650 EUR
Course Part Number: 760902
Description
This Advanced Verification Jumpstart will be the start for Design and Verification Engineers to learn more about new methods in advanced verification using SystemVerilog Assertions (SVA) and Functional Coverage.
Hands-On Labs
Throughout this course, extensive hands-on lab exercises provide you with practical experience using either ModelSim DE or Questa software.
Audience
- Design Engineers
- Verification Engineers
Prerequisites
VHDL or Verilog experience
Course Outline
In this course you will learn how Assertion Based Verification can help you to become more productive in your system level verification and debug of your design. A detailed overview on what assertions are and how they should be applied to your design will be given. Also covered are the specific language features in System Verilog that enable you to define the assertions and properties and how to bind them to your design. During the training you will also learn how to use ModelSim DE or Questa to simulate a design using SV Assertions, and how we can leverage this to verify or enhance the functional coverage of your design.
For more information:
InnoFour BV
Twentepoort Oost 61-02
7609 RG ALMELO
The Netherlands
tel +31 546 454 530
fax +31 546 453 006