Assertion Based Verification for FPGA and IC Design Seminar
Eindhoven, Netherlands – Apr 14, 2010 Overview
Industry Perspective and Opportunities in Assertion-Based Verification
A wealth of material has been published over the past fifteen years specifically related to the theory and technical aspects of property languages and assertion-based techniques. However, as any field of study matures, it becomes necessary to determine if the theories, algorithms, and concepts have grown beyond the bounds of research to become an integral solution to a problem in industry. To understand any solution, it is necessary to understand the problem. For example, debugging, on average, has grown to consume more than 60 percent of today's SoC verification effort. Clearly, this is a topic the industry must address, and some organizations have done just that. Those that have adopted an assertion-based verification (ABV) methodology have seen a significant reduction in simulation debugging time (as much as 50 percent) due to improved observability.
What You Will Learn
- Assertion-based Verification techniques
- Roadmap for evolving your organizations ABV Capabilities
- Degugging with Assertions
- Effective Coverage techniques
- Process for analyzing your data and providing both detailed and management level report
Who Should Attend
FPGA & ASIC Design and Verification Engineers and Managers
- 8:30 - 9:00 Check in and Registration
- 9:00 - 9:50 Industry Perspective and Opportunities in Assertion-Based Verification, Harry Foster
- 10:00 - 10:50 Effective Coverage using Assertions
- 11:00 - 11:50 Advanced Debugging with Assertions
- 12:00 - 12:30 Lunch
- 12:30 - 3:00 SystemVerilog Assertion Coding Tricks, Debugging Techniques and Bind Files, Cliff Cummings
ABOUT THE PRESENTERS
Cliff Cummings is President of Sunburst Design, Inc., a company that specializes in world-class Verilog, SystemVerilog and synthesis training.
Cliff has presented more than 100 SystemVerilog seminars and training classes and was the featured speaker at the world-wide SystemVerilog NOW! seminars in 2003.
Cliff has been an active participant on every IEEE & Accellera Verilog, Verilog Synthesis, and SystemVerilog committee, and has presented more than 40 papers on Verilog & SystemVerilog related design, synthesis and verification techniques. 17 were voted "Best Paper" and are downloaded by engineers world-wide.
Cliff holds a BSEE from Brigham Young University and an MSEE from Oregon State University.
Harry Foster is Chief Verification Scientist for Mentor Graphics' Design Verification Technology Division. He holds multiple patents in verification and has co-authored five books on verification--including the 2008 Springer book Creating Assertion-Based IP. Harry was the 2006 recipient of the Accellera Technical Excellence Award for his contributions to developing industry standards, and was the original creator of the Accellera Open Verification Library (OVL) standard.