Automating Post-Route Verification for Multi-Gigabit Channels
Performing post-layout verification of multi-gigabit SerDes channels is a challenging but necessary task, because even the most detailed pre-layout simulation studies and routing guidelines can’t anticipate everything. Designs that meet detailed routing requirements can still fail due to discontinuities and resonances that couldn’t have been anticipated.
The large numbers of channels in modern designs makes post-route verification difficult – each channel must be modeled and analyzed individually, which requires an automated, efficient process to be successful. Once modeled, each channel must be analyzed for compliance with protocol requirements in the same automated fashion.
This webinar will discuss requirements for effective SerDes channel post-route verification and show how they can be achieved.
What You Will Learn
- Different types of SerDes compliance analysis
- Compliance analysis using Channel Operating Margin (COM)
- Differences between COM analysis and IBIS-AMI simulation
- Different forms of Tx/Rx equalization and when they are effective
- How to identify areas of a SerDes channel that require 3D EM modeling
- How to isolate individual physical effects and determine their effect on system margin
- How to perform post-layout “what if” analysis for SerDes channels
- How to determine the impact of crosstalk on SerDes channel margins
Who Should Attend
- PCB/System Designers
- Engineering Managers
- Signal Integrity Specialists
- PCB Layout Designers
Live Webinar: Automating Post-Route Verification for Multi-Gigabit Channels
Tuesday the 8th of September 2020
3:00 PM - 4:00 PM CEST
This webinar explores the different aspects of serial channel design planning and analysis from the pre-layout standpoint, using simulation to develop a detailed set of layout rules. Design of detailed geometries requiring 3D EM simulation is explored, showing how to assess design alternatives and maximize overall channel margin.How Integrated FPGA-PCB I/O Co-Design Accelerates PCB Design and Reduces Costs
In this webinar you will learn that modern FPGA I/O optimization helps you not only accelerate design time-to-market, but also reduces manufacturing costs.