Evolve Your FPGA Verification Methodology with Formal & Clock Domain Crossing
Attention FPGA Designers
Mentor Graphics, together with our partners InnoFour, Saros and TRIAS, invite you to attend this online seminar on the following date:
Tuesday November 15.
What You Will Learn
Learn how to rapidly identify, debug and fix logic, functional and CDC related issues in your design.
About the Presenter
Stefan joined Mentor Graphics in 2014 for supporting the distribution channel in the whole HDL area with focus on functional verification. Prior to that, Stefan worked as a verification engineer for Ericsson in Nuremberg, Germany. The main focus of his work was verifying parts of an ASIC by using an OVM/UVM test environment. Stefan has a master’s degree in Electrical Engineering from the Friedrich-Alexander-University Erlangen-Nuremberg.
Tuesday the 15th of November 2016
14:00 - 15:00 CEST
Create High Quality Documentation while Saving Time with BluePrint-PCB.UVM and VIP - Evolve Your FPGA Verification Methodology
Attend this free online session to learn how the UVM Framework and Questa Verification IP can provide you the needed solution to achieve your verification goals.