19 October 2016

UVM and VIP – Evolve Your FPGA Verification Methodology

Overview

Attention FPGA Designers

Did your last FPGA design stretch beyond the project schedule?

Did your last FPGA have post production identified defects?

Did your last FPGA require more than 3 iterations of lab debug?

Attend this free online session to learn how the UVM Framework and Questa Verification IP can provide you the needed solution to achieve your verification goals.

Mentor Graphics, together with our partners InnoFour, Saros and TRIAS, invite you to attend this online seminar on the following date:

Monday November 14.

What You Will Learn

Learn how to rapidly create a UVM Framework environment and how to incorporate the UVM Framework environment created by the Questa Verification IP Configurator.

About the Presenter

Stefan Bauer

Stefan joined Mentor Graphics in 2014 for supporting the distribution channel in the whole HDL area with focus on functional verification. Prior to that, Stefan worked as a verification engineer for Ericsson in Nuremberg, Germany. The main focus of his work was verifying parts of an ASIC by using an OVM/UVM test environment. Stefan has a master’s degree in Electrical Engineering from the Friedrich-Alexander-University Erlangen-Nuremberg.

Details

Monday the 14th of November 2016

14:00 - 15:00 CEST

Evolve Your FPGA Verification Methodology with Formal & Clock Domain Crossing

Attend this free online session to learn how Questa Formal with Autocheck and Clock Domain Crossing (CDC) can provide you with the needed solution to achieve your verification goals

Back to overview

PTC / User Benelux Event 2016

We are happy to announce that this year InnoFour will be present at the 20th Benelux PTC/USER Conference. We invite you to attend this event and meet the InnoFour representatives Peter Bakker and Ni Wang.