UVM and VIP – Evolve Your FPGA Verification Methodology
Attention FPGA Designers
Mentor Graphics, together with our partners InnoFour, Saros and TRIAS, invite you to attend this online seminar on the following date:
Monday November 14.
What You Will Learn
Learn how to rapidly create a UVM Framework environment and how to incorporate the UVM Framework environment created by the Questa Verification IP Configurator.
About the Presenter
Stefan joined Mentor Graphics in 2014 for supporting the distribution channel in the whole HDL area with focus on functional verification. Prior to that, Stefan worked as a verification engineer for Ericsson in Nuremberg, Germany. The main focus of his work was verifying parts of an ASIC by using an OVM/UVM test environment. Stefan has a master’s degree in Electrical Engineering from the Friedrich-Alexander-University Erlangen-Nuremberg.
Monday the 14th of November 2016
14:00 - 15:00 CEST