04 December 2017


FPGA-forum is a yearly event for the Norwegian FPGA community. FPGA-designers, project managers, technical managers, researchers, final year students and the major vendors gather for a two-day focus on FPGA. There will be presentations from the Norwegian industry about methodology and practical experience, – the universities will present new and exciting projects, and the vendors will have technical presentations with a minimum of marketing.

At the exhibition, you can evaluate tools and technology from the leading vendors. FPGA-forum also provides an excellent opportunity to meet and exchange experience with the Norwegian FPGA-community – during the breaks – and during the official dinner party on Wednesday.


Besides the exhibition, InnoFour will host this presenation:


Mastering Clock Domain Crossing challenges in FPGA Design - by Stefan Bauer, Mentor Graphics
Metastabilty from the intermixing of multiple clock signals is not modeled by simulation. Unless you leverage exhaustive, automated Clock Domain Crossing (CDC) analyses to identify and correct problem areas, you will inevitably suffer unpredictable behavior when you go to the lab or when the FPGA is used in the field. Bottom-line: automated CDC verification solutions are mandatory for multi-clock designs.
Designers increasingly use advanced multi-clocking architectures to meet the high-performance and low-power requirements of their chips. An RTL or gate-level simulation of a design that has multiple clock domains does not accurately capture the timing related to the transfer of data between clock domains. As a consequence, simulation does not accurately predict silicon behavior, and critical bugs may escape the verification process.
The Questa CDC Solutions identify errors that have to do with clock domain crossings – signals (or groups of signals) that are generated in one clock domain and consumed in another. It does so with structural analysis and recognition of clock domains, synchronizers, and low power structures (via UPF); and with generation of metastability models for reconvergence verification. The technology checks all potential failure modes and presents to the user familiar schematic and waveform displays. Additionally, in concert with simulation this technology can be used to inject metastability into functional simulation to verify the DUT correctly processes asynchronous clocks.


Check this link for the FPGA Forum Program





14th and 15th of February 2018



Radisson Blu Royal Garden Hotel, Kjoepmannsgt. 73, Trondheim



09:00 - 17:00 hr