FPGA-forum is a yearly event for the Norwegian FPGA community. FPGA-designers, project managers, technical managers, researchers, final year students and the major vendors gather for a two-day focus on FPGA. There will be presentations from the Norwegian industry about methodology and practical experience, – the universities will present new and exciting projects, and the vendors will have technical presentations with a minimum of marketing.
At the exhibition, you can evaluate tools and technology from the leading vendors. FPGA-forum also provides an excellent opportunity to meet and exchange experience with the Norwegian FPGA-community – during the breaks – and during the official dinner party on Wednesday.
We also want to invite you the to the presentation by Faïçal Chtourou, DVT Field Application Engineer:
Using Python for a high-quality reusable verification environment.
Constrained randomization and functional coverage have recently become crucial elements to a successful verification of FPGA and ASIC design.
SystemVerilog and UVM framework is the de-facto standard for verification. Still, due to a high learning time/benefit ratio, many users preferred to look into other alternatives such as UVVM/OSVM. Lately, Python has emerged as a third option, and it is gaining interest for its obvious advantages (easy language, big community, extensive library …) The purpose of this presentation is to show you how we can build a high-quality reusable verification environment using Python Libraries/Framework.
Check this link for the FPGA Forum Program.
7th and 8th of September 2022
Royal Garden Hotel, Kjoepmannsgt. 73, Trondheim, 7010, Norway
09:00 - 17:00 hr