Technical Workshop with Inventas, Siemens and InnoFour
Welcome to an afternoon at Inventas Oslo, tailored for FPGA-developers. Together with Inventas and Siemens EDA, we invite you to a free, practical session where theory meets real-world application. Bring your laptop and your own code, and gain hands-on experience with advanced verification techniques. We wrap up the day with an afterwork, where conversations can continue in a more relaxed setting.
FPGA verification with advanced debugging, simulation flows and modern test-bench methodologies
Through these sessions with presentations and a hands-on workshop, we will focus on practical application, giving you tools and techniques you can take directly into your own projects. This afternoon is also a great opportunity to exchange experiences with others working in FPGA-development across industries.
You will learn:
- Efficient simulation flows using the Questa environment
- How to structure and streamline build-and-run processes
- Advanced debugging techniques using Visualizer
- Performance analysis and bottleneck identification
- Coverage analysis and verification closure
- Practical approaches to structured testbench development using UVVM
- How to automate regression testing workflows
About the sessions
- Hands-on workshop:
Questa Simulator Hidden Gems & Advanced Debugging with Visualizer; by Faïçal Chtourou - DVT Field Application Engineer at Siemens EDA
This session provides a practical overview of advanced capabilities in the Questa simulation environment. Participants will work with QIS two‑step and three‑step flows and learn how to streamline build‑and‑run processes using the qrun utility. The workshop then focuses on advanced debugging techniques with Visualizer, followed by performance analysis using the Profiler to identify and resolve simulation bottlenecks. Finally, we will cover coverage review and closure methods to complete the verification workflow.
Participants should bring their own laptops; all required tools and lab environments will be provided onsite.
- Presentation:
Simple and Efficient FPGA Verification with UVVM and HDLRegression; by Marius Elvegård, Senior FPGA Developer & Discipline leader Digital at Inventas.
This session demonstrates how to create a UVVM-based test-bench step-by-step, and how HDLRegression can be used to automate simulation and regression workflows. The focus is on simplicity, scalability, and efficiency, helping you reduce manual work and increase confidence in your designs.
- Guest lecture:
Starting on the right foot with cocotb by Yngve Hafting; Lecturer at the Research Group for Robotics and Intelligent Systems at Oslo University
The session focuses on how cocotb manages timing and the event queue, illustrated with concrete code examples. You will also learn key principles that ensure predictable behavior in both stimulus generation and checker algorithms.
Practical information
This is a collaboration between Inventas, Siemens and InnoFour, combining tools, methodology, and hands-on experience. Check this link for the complete agenda of the afternoon and sign up for free.
Details
When
Tuesday May 6, 2026
Where
Inventas AS, Kjølberggata 21, 0653 Oslo Norway
Time
11:30 - 20:00 hr
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