FPGA Verification Forum 2012 with Harry Foster
InnoFour and Mentor Graphics are pleased to invite you to our 2012 FPGA Verification Forum. As today’s FPGAs are where ASICs were 10 years ago, you can no longer meet schedules and deliver designs on time with a simple milestone of being “in the lab”. This event will take you on a journey to employ new techniques to get your projects out faster and with fewer problems. It is a like a train journey with various stops. You can choose to get off at the first stop or go all the way to the last stop. Either way, you will benefit and reach your ultimate goal.
This technical conference will help all engineers or managers involved in verification, to gain more from their ModelSim or Questa environment and introduce them to the latest methodologies for the verification of complex FPGA devices.
During the event the following topics will be covered:
- Why do you need a Verification Process,
- Three Steps to injecting Automation
- Reduce debug Time by 50%
- Understand where you are in the Verification Process
- Build an effective Testbench Infrastructure
- ModelSim GUI Essentials - with Demonstrations
- Performance Tuning: Tips & Tricks
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The key presentations will be done by Harry Foster, who is chief verification scientist for Mentor Graphics’ Design Verification Technology Division. He holds multiple patents in verification and has co-authored five books on verification -- including the 2008 Springer book Creating Assertion-Based IP. Harry was the 2006 recipient of the Accellera Technical Excellence Award for his contributions to developing industry standards, and was the original creator of the Accellera Open Verification Library (OVL) standard. |
The FPGA Verification Forum 2012 will be held on Monday the 24th of September 2012 at the STRIP Conference Center on the High Tech Campus in Einhoven.
Details:
- What: FPGA Verification Forum 2012 with Harry Foster
- When: Monday, September 24, 2012
- Where: the STRIP Conference Center, High Tech Campus 1, Eindhoven
- Time: 08.30 - 17.00 hr CET
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