Live Webcast: Accelerating RTL Design Reuse

Overview
To meet the schedules and demands for complex ASIC and FPGA design projects, reusing HDL code as building blocks for new and next generation designs has become a common practice. Before committing pre-existing HDL blocks for reuse however, a design team often goes through a process to determine the code quality and builds an understanding of how the code will be incorporated into the new project. 

What You Will Learn
This session will offer guidelines for code reuse and how to apply some practical approaches to accelerate the effort.

Who Should Attend

• Engineers
• Engineering Managers

Details:

• What: Accelerating RTL Design Reuse
• When: Thursday 18th of Februari 2010
• Where: Online
• Time: 16:00 PM CET
• Duration: 1 hour
• Registration: E-mail